Direct Link Synchronization Between Co-Processors to Reduce CPU Load
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Solution Overview
Problem
Current system-on-chip (SoC) processors experience screen tearing issues due to conflicts between the display controller and buffer updates, particularly during frequent updates in video playback or gaming, which existing solutions like the flip method do not fully address.
Innovation Solution
Implementing a direct link for synchronization communications between co-processor graphic data producers and consumers, such as the 3D engine and display controller, to bypass the central processing unit, allowing for efficient coordination and reducing CPU involvement, thereby minimizing screen tearing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the display controller scans the buffer while it is being updated, then the buffer update frequency can be increased, but screen tearing occurs due to read-write conflicts
Solution Approach 1:
The patent implements a flip buffer method where the back buffer is prepared in advance with new screen content before the display controller finishes scanning the front buffer. A vertical blanking interval (VBLANK) interrupt is used to trigger the buffer swap at the optimal moment, ensuring that the display controller reads from a stable buffer while the other buffer is being updated, thus preventing screen tearing while maintaining high update frequency
Solution Approach 2:
The patent introduces a buffer management mechanism with front buffer and back buffer as intermediaries between the display controller and the rendering system. This intermediary structure allows the display controller to continuously scan one buffer while the rendering system updates the other buffer in parallel, eliminating read-write conflicts and enabling simultaneous operation without screen tearing
2Reliability
If the central processing unit handles synchronization messages between co-processors, then coordination between cores is achieved, but CPU load increases and performance decreases
Solution Approach 1:
The patent segments the synchronization handling responsibility from the CPU by implementing dedicated synchronization mechanisms at the co-processor level. The display controller and 3D engine can directly coordinate through buffer pointers and synchronization signals without requiring CPU intervention for each synchronization event, reducing CPU load while maintaining reliable inter-core coordination
Solution Approach 2:
The patent enables co-processors to self-coordinate through direct communication mechanisms. The display controller can autonomously detect when the back buffer is ready for scanning by monitoring buffer readiness signals, and the 3D engine can autonomously update buffer pointers without CPU mediation. This self-service approach allows synchronization to occur independently of the CPU, improving overall system performance while maintaining coordination reliability
Data Source
AI summary
Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data producer and a co-processor graphic data consumer via a direct link without passing such communications through the central processing unit.