Direct Memory Mapped Control Registers for Multi-Process Protection
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Solution Overview
Problem
Current hardware-based functional verification systems face challenges in providing multi-process protection, leading to increased complexity in device drivers, runtime overhead, and potential information leakage due to the reliance on software behavior for access control.
Innovation Solution
A method and system utilizing direct memory mapped control registers, where each execution unit in a controller switch has a set of control registers with unique accessible addresses, allowing exclusive access to processes and denying access until the registers are released, thereby eliminating the need for complex device driver access control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based access control mechanisms are used in device drivers, then multi-process protection can be provided, but device driver complexity increases and runtime overhead is introduced
Solution Approach 1:
The patent extracts the access control logic from the device driver software layer and implements it directly in hardware through control registers. Each execution unit has dedicated control registers that are directly accessible by processes, eliminating the need for complex software-based access control mechanisms in the device driver while maintaining multi-process protection.
Solution Approach 2:
The patent introduces control registers as an intermediary hardware structure between processes and execution units. These registers serve as the mediator that automatically enforces access control policies, replacing the need for complex software mediation in device drivers and reducing both driver complexity and runtime overhead.
2Reliability
If software-based access control mechanisms are used in device drivers, then multi-process protection can be provided, but runtime overhead increases
Solution Approach 1:
The patent extracts access control functionality from software device drivers and implements it in hardware control registers. This extraction eliminates the runtime overhead associated with software-based access control while maintaining multi-process protection, as the hardware registers automatically enforce access policies without software intervention.
Solution Approach 2:
The control registers are designed to automatically manage access control without requiring software-based mediation. The hardware structure itself provides the access control service, eliminating the need for runtime software checks and reducing time loss while maintaining protection against information leakage.
3Ease of operation
If software-based access control is used, then access management can be implemented, but information leakage may occur due to reliance on software behavior
Solution Approach 1:
The patent extracts access control from software behavior and implements it in hardware control registers. This hardware-based approach eliminates the reliability issues of software-based access control, preventing information leakage while maintaining ease of operation through direct process access to dedicated registers.
Solution Approach 2:
The patent uses simple, dedicated control registers for each execution unit that provide robust access control. These hardware structures provide reliable, leak-proof access management without the complexity and potential failures of software-based solutions, ensuring information security through hardware-enforced isolation.
Data Source
AI summary
A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit. A second access request to access the execution unit received from a second process is denied by checking the assignment of the set of direct accessible addresses to the set of control registers of the execution unit while the first process retains exclusive access to the execution unit.