Direct Memory Data Transfer on Shared Bus
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Solution Overview
Problem
Existing data transfer techniques between devices on a shared bus require significant involvement from memory controllers, leading to inefficiencies in resource usage, processing time, and power consumption.
Innovation Solution
Implementing a direct data transfer method using a shared bus, where a controller provides source and target addresses, read commands, and enable signals, allowing memory devices to transfer data independently, reducing the controller's involvement and optimizing system resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory controller reads data from source device to internal data storage and then writes to target device, then data transfer between different memory types is enabled, but controller involvement increases and processing time increases
Solution Approach 1:
The patent extracts the data transfer function from the memory controller by enabling direct peer-to-peer data transfer between memory devices. The controller only initiates the transfer by providing source and target addresses, then the actual data movement occurs independently between devices, removing the time-consuming intermediate storage and processing steps from the controller.
Solution Approach 2:
The patent introduces a shared bus as an intermediary communication channel that enables direct data transfer between memory devices. This bus serves as a mediator that allows devices to exchange data independently without requiring the controller to act as an intermediate storage point, thus reducing processing time while maintaining transfer capability.
2Productivity
If a memory controller is fully involved to facilitate data transfer between devices, then data transfer is enabled, but controller efficiency decreases and resource usage increases
Solution Approach 1:
The patent implements self-service by enabling memory devices to perform data transfer operations independently without continuous controller intervention. Once the controller provides the initial parameters (source address, target address), the source and target devices autonomously complete the data transfer, freeing the controller for other tasks and improving overall system productivity.
Solution Approach 2:
The patent extracts the data transfer execution function from the memory controller, leaving the controller with only the initiation role. This separation reduces controller complexity and involvement while maintaining the ability to facilitate transfers between different device types, as the actual data movement is handled directly between peer devices.
3Productivity
If data is transferred through controller internal data storage, then data transfer between devices is enabled, but internal memory requirements increase and power consumption increases
Solution Approach 1:
The patent removes the requirement for controller internal data storage by enabling direct data paths between source and target devices. Data flows directly through the shared bus without being copied into or processed through the controller's internal memory, eliminating the power consumption associated with maintaining and accessing controller buffers while preserving full data transfer capability.
Solution Approach 2:
The shared bus acts as an energy-efficient intermediary that enables direct data transfer between devices without requiring expensive and power-consuming internal storage in the controller. This bus-mediated approach maintains productivity by enabling all necessary data transfers while significantly reducing the power usage associated with controller internal memory operations.
Data Source
AI summary
Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.