Direct Memory Transfer Circuit for Processor-Independent Subregion Transfers
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Solution Overview
Problem
Existing memory circuits, including intelligent or 'smart' memory circuits, often require processor intervention for data transfers and reorganization, leading to inefficiencies in data exchange and computational load.
Innovation Solution
A direct data transfer circuit between memory circuits that receives specific instructions from a processor, allowing for controlled data transfers and reorganization without processor intervention, using SET_REGION and transfer instructions to define sub-regions and execute multiple transfers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfers are performed through the processor, then data exchange between memory circuits is achieved, but processor load and data exchange channel usage increase
Solution Approach 1:
A dedicated direct data transfer circuit is introduced as an intermediary device between the first and second memory circuits. This circuit receives specific instructions from the processor, decodes them, and autonomously controls data transfers between memory circuits, eliminating the need for processor intervention in each transfer operation while maintaining controlled and efficient data exchange
Solution Approach 2:
The data transfer function is extracted from the processor and implemented as a separate, dedicated direct data transfer circuit. This extraction allows the processor to focus on computational tasks while the specialized circuit handles data movement and reorganization between memory circuits
2Productivity
If data is transferred in large blocks between memory circuits, then transfer efficiency improves, but flexibility in defining transfer regions decreases
Solution Approach 1:
The memory space is segmented into definable sub-regions through the SET_REGION instruction, which allows the direct data transfer circuit to operate on specific portions of memory rather than requiring entire memory blocks to be transferred. This segmentation enables flexible region definition while maintaining efficient bulk transfer capabilities within each defined region
Solution Approach 2:
The system dynamically adapts between different transfer granularities by allowing the processor to define sub-regions of varying sizes through SET_REGION instructions. The direct data transfer circuit can then execute multiple successive transfer instructions within the same defined sub-region, providing both flexibility in region definition and efficiency in bulk operations
Data Source
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AI summary
This description relates to a system comprising at least a first and a second memory circuit; and - a direct data transfer circuit which is adapted to receive specific instructions from an external processor, and to decode specific instructions comprising: - a specific SET_REGION instruction for defining a subregion in the first memory circuit to or from which data will be transferred; and - a specific transfer instruction between said subregion and the second memory circuit, the specific transfer instruction comprising a first address field containing the relative coordinates, in said subregion, of a first reference cell.