Direct Metal Gate Patterning for FinFET Threshold Voltage Control
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Solution Overview
Problem
Conventional methods for adjusting threshold voltages in field effect transistors (FETs), particularly in FinFET technology, face challenges such as dopant fluctuations and performance degradation due to the three-dimensional geometry and static electricity of semiconductor fins, making it difficult to achieve different threshold voltages without compromising device performance.
Innovation Solution
The approach involves direct metal gate patterning with selectively incorporated metal layers of different work functions in the gate stack portions to achieve varying threshold voltages, allowing for independent control of threshold voltages in different FETs without degrading device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel doping is used to adjust threshold voltage in FinFETs, then threshold voltage can be modified, but dopant fluctuations and threshold voltage variation occur due to three-dimensional geometry, degrading device performance
Solution Approach 1:
The patent changes the physical parameter of the gate electrode material by using different work function metals (e.g., tungsten for higher threshold voltage, titanium nitride for lower threshold voltage) instead of changing doping concentrations. This allows precise control of threshold voltage without introducing dopant fluctuations that degrade device performance in three-dimensional FinFET structures.
Solution Approach 2:
The patent applies different metal materials with specific work functions to different gate electrode regions to achieve locally optimized threshold voltages. By selectively placing high work function metal in some FinFETs and low work function metal in others, the invention creates local quality variations that enable different threshold voltage characteristics in different device regions without affecting overall device reliability.
2Manufacturing precision
If doping concentration in channel region is increased to raise threshold voltage, then threshold voltage increases, but carrier mobility decreases and device performance deteriorates
Solution Approach 1:
The patent changes the controlling parameter for threshold voltage from doping concentration to gate electrode work function. By selecting metals with appropriate work functions (e.g., tungsten at 4.5-5.0 eV for high threshold voltage, titanium nitride at 4.0-4.5 eV for low threshold voltage), the invention achieves precise threshold voltage adjustment without increasing doping concentration, thereby preserving carrier mobility and device speed.
3Manufacturing precision
If highly-doped ions are introduced in channel region, then threshold voltage increases, but device resistance increases due to compensation of ions in source/drain region
Solution Approach 1:
The patent changes the mechanism for threshold voltage control from channel doping to gate electrode material selection. This eliminates the need to introduce highly-doped ions into the channel region, thereby preventing the compensation effect in source/drain regions and avoiding increased device resistance. The work function of the gate electrode directly controls threshold voltage without affecting doping profiles in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively allows for the manipulation of threshold voltages in multiple FETs with different requirements, such as SRAM and logic transistors, without compromising carrier mobility or device reliability, thereby improving the performance and functionality of semiconductor structures.
Implementation Method 1
The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions of a gate stack
Data Source
AI summary
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.