Direct Logical to Physical Address Mapping in NVRAM Cache
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Solution Overview
Problem
Current storage systems face inefficiencies in utilizing non-volatile random access memory (NVRAM) devices as cache devices due to indirect mapping methods that are resource-intensive and lead to increased write amplification, reduced device lifespan, and higher costs, while also failing to effectively manage data consistency and access patterns.
Innovation Solution
Implementing a direct mapping method between logical and physical addresses in an NVRAM-based storage subsystem, using a hash-based approach to equalize mapping probabilities and manage data access by determining the state of cached data (updated or non-updated) to optimize cache performance through eviction policies based on access intensity and importance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If indirect mapping methods are used in NVRAM cache devices, then data can be stored and accessed, but overhead increases, write amplification increases, and device lifespan decreases
Solution Approach 1:
The patent extracts and eliminates the intermediate mapping layer from the address translation process. Instead of using indirect mapping methods that require multiple translation steps, the invention implements direct mapping where logical addresses are directly translated to physical addresses in the NVRAM cache device, removing unnecessary complexity and overhead while maintaining data accessibility
Solution Approach 2:
The patent changes the mapping dimension from indirect multi-step translation to direct one-step translation. By establishing a direct correspondence between logical addresses and physical addresses in NVRAM, the system eliminates the intermediate mapping layer, reducing computational overhead and simplifying the address translation process
2Reliability
If indirect mapping methods are used in NVRAM cache devices, then data can be stored, but write amplification increases and device lifespan decreases
Solution Approach 1:
The patent removes the intermediate mapping operations that cause redundant write amplification. By implementing direct mapping between logical and physical addresses, the system eliminates unnecessary data movement and translation steps, thereby reducing write amplification and extending NVRAM device lifespan
Solution Approach 2:
The patent changes the mapping parameter from indirect multi-stage translation to direct one-stage translation. This parameter change reduces the number of write operations required, lowering write amplification and improving device reliability and lifespan
3Productivity
If indirect mapping methods are used, then data can be accessed, but overhead increases and performance decreases
Solution Approach 1:
The patent extracts and eliminates the intermediate mapping operations that create access overhead. By implementing direct mapping where logical addresses are directly translated to physical addresses in NVRAM, the system removes unnecessary processing steps, reducing access overhead and improving cache performance
Data Source
AI summary
Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.