Direct Pad-Contact Chip Assembly Without Ball Bump Misalignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods of mounting semiconductor chips onto substrates using ball bumps can lead to misalignment due to thermal stress, and existing bumpless techniques face challenges in reliably connecting chip pads to contact pads without thermal processes.
Innovation Solution
The semiconductor device employs a surface activation process under high vacuum and room temperature to remove oxide films and adsorbates from chip and contact pads, allowing for direct and firm contact between protruding chip pads and contact pads without thermal processes, ensuring reliable electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ball bumps are used for mounting semiconductor chips, then mechanical strength is improved, but misalignment occurs due to thermal stress
Solution Approach 1:
The patent removes the ball bump structure entirely, extracting the problematic thermal expansion component from the system. Instead of using spherical bumps that expand and contract with temperature changes, the invention uses direct pad-to-pad contact with carefully controlled interlayer film thickness to achieve both mechanical strength and alignment precision without thermal stress-induced misalignment.
Solution Approach 2:
The patent changes the critical parameter of interlayer film thickness to a specific range (50-200 nm) to achieve the desired outcome. By controlling the interlayer film thickness within this narrow range, the invention ensures direct contact between chip pads and substrate contact pads while accommodating thermal expansion differences, thereby maintaining both mechanical strength and alignment precision across temperature variations.
2Device complexity
If bumpless mounting technique is used, then manufacturing complexity is reduced, but reliable connection between pads is difficult to achieve
Solution Approach 1:
The patent achieves reliable bumpless connection by precisely controlling the interlayer film thickness parameter within 50-200 nm. This specific thickness range ensures that pads make direct contact without requiring complex bump formation processes, while simultaneously guaranteeing sufficient mechanical and electrical reliability through intimate pad-to-pad contact.
Solution Approach 2:
The invention performs preliminary preparation by pre-forming pads with protruding structures and controlling interlayer film thickness before the mounting process. This preliminary action ensures that when the chip is placed on the substrate, direct contact between pads occurs automatically without requiring complex real-time adjustment or additional connection steps, thereby achieving both simplicity and reliability.
3Strength
If thermal processes are used for bonding, then connection strength is improved, but oxide films and adsorbates interfere with direct contact
Solution Approach 1:
The patent employs an inert atmosphere environment during the mounting process to prevent oxide film formation and adsorbate contamination on pad surfaces. By controlling the atmospheric environment, the invention enables direct metal-to-metal contact between pads without the interfering layers that would otherwise require thermal processes to remove, thereby achieving strong connections without thermal stress-induced misalignment.
Solution Approach 2:
The invention replaces thermal bonding processes with a mechanical direct-contact system. Instead of using heat to remove oxide films and achieve bonding, the patent uses precisely controlled interlayer film thickness and pad protrusion design to enable direct mechanical contact between pads in an inert atmosphere, eliminating the need for thermal processes and their associated harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method eliminates misalignment issues and provides a robust, reliable electrical connection between chip and substrate pads, enhancing the reliability and precision of semiconductor device assembly.
Implementation Method 1
A surface activation process under high vacuum and room temperature to remove oxide films and adsorbates from chip and contact pads
Data Source
AI summary
A semiconductor device includes a semiconductor chip including a wiring layer formed on a first side, a first pad formed so as to protrude from a surface of a passivation film on the first side, and an interlayer film formed between the first side and the wiring layer on one side and the passivation film and the first pad on another side, and a mounting substrate including a second pad on the second side, and the first pad and the second pad are in contact with each other. A thickness of the interlayer film between the wiring layer and the first pad is 0.5 to 2.8 μm. The first pad is disposed between formation regions of internal circuits provided on the semiconductor chip.