DRAM Page Activation via Direct Processor Path
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Solution Overview
Problem
Memory-access latency in computing systems is a significant performance bottleneck due to latencies associated with DRAM page activation, cache coherency, and interconnect operations, which existing technologies have not effectively addressed.
Innovation Solution
A system and method that utilize out-of-band signaling to parallelize DRAM operations and coherency operations by allowing processors to send speculative page activation requests directly to memory controllers, bypassing the interconnect, thereby masking or hiding these latencies and activating DRAM pages only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory access requests are sent through the interconnect, then cache coherency operations can be performed, but memory-access latency increases due to interconnect arbitration and serialization
Solution Approach 1:
The patent segments the memory access path into two independent channels: a first path through the interconnect for cache coherency operations, and a second direct path to the memory controller for page activation requests. This segmentation allows simultaneous execution of coherency checks and page activation, eliminating the serialization bottleneck and reducing overall memory-access latency while maintaining cache coherency requirements.
2Loss of time
If DRAM page activation is performed before memory access, then memory-access latency is reduced, but system complexity increases due to speculative operations
Solution Approach 1:
The patent implements preliminary action by sending page activation requests speculatively through the second direct path before the actual memory access is needed. The processor can dynamically determine whether to send these speculative requests based on access patterns. If the speculation is correct, the page is already activated when needed, reducing latency. If incorrect, the speculative request is simply ignored, avoiding unnecessary complexity.
3Loss of time
If multiple paths are provided for memory requests, then latency is reduced through parallel operations, but routing complexity increases
Solution Approach 1:
The patent extracts the page activation function from the interconnect routing path and creates a separate direct path to the memory controller. This extraction allows page activation requests to bypass the complex interconnect arbitration and serialization logic, using a simpler direct routing mechanism. The interconnect remains dedicated to cache coherency operations, maintaining its complexity only where necessary while enabling parallel execution with reduced routing overhead.
Data Source
AI summary
A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.