Direct QLC Programming via Segmented TLC and Fine Stages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-level cell (MLC) programming in non-volatile memory requires large write buffers and unbalanced state coding, leading to inefficient memory cost and bit error rate (BER) imbalances, which are exacerbated by the need for excessive error correction code (ECC) redundancy and sensitivity to ungraceful shutdowns.
Innovation Solution
A direct quad-level cell (QLC) programming scheme using a two-stage approach, where three pages are programmed in a triple-level cell (TLC) phase and one extra page in a Fine stage with non-balanced 2-3-2-8 grey coding, reducing the write buffer requirement and achieving balanced BER and read time across pages, while being robust to ungraceful shutdowns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-level cell (MLC) programming is used with unbalanced state coding, then memory can be programmed, but write buffer size increases and cost efficiency decreases
Solution Approach 1:
The patent segments the QLC programming process into two distinct stages: a first programming stage that programs three pages of data, and a second programming stage that programs a fourth page. This segmentation allows each stage to be optimized independently, with the first stage using balanced state coding and the second stage handling the remaining data, thereby reducing the write buffer size requirement while maintaining programming reliability
Solution Approach 2:
The patent changes the programming parameters by using different programming voltages and pulse widths for the first and second programming stages. The first programming stage uses parameters optimized for programming three pages, while the second stage uses adjusted parameters for programming the fourth page, enabling efficient QLC programming with reduced buffer requirements
2Reliability
If excessive error correction code (ECC) redundancy is added to handle unbalanced state coding, then bit error rate (BER) improves, but memory density and cost efficiency worsen
Solution Approach 1:
The patent applies local quality by using balanced state coding specifically for the first three pages programmed in the first stage, which ensures uniform error distribution and reduces the need for excessive ECC redundancy. The balanced state coding maintains consistent bit error rates across these pages, allowing for more efficient error correction with less redundancy
Solution Approach 2:
The patent performs preliminary action by programming three pages with balanced state coding in the first stage before programming the fourth page. This preliminary programming with balanced coding establishes a foundation with lower and more uniform error rates, reducing the burden on ECC for the overall data set
3Quantity of substance
If conventional programming processes are used, then all data bits can be stored, but programming time and complexity increase
Solution Approach 1:
The patent segments the QLC programming operation into two efficient stages that can be executed in sequence. The first programming stage programs three pages of data using optimized parameters, and the second programming stage programs the fourth page. This segmentation enables parallel processing opportunities and optimizes the programming timeline, reducing total programming time while maintaining full data storage capacity
Solution Approach 2:
The patent ensures continuity of useful action by designing the two-stage programming process to flow seamlessly from the first stage to the second stage without requiring intermediate data retrieval or buffer clearing operations. The continuous programming action maximizes the utilization of programming circuits and reduces idle time, thereby reducing overall programming time
Data Source
AI summary
A storage system and method for direct quad-level cell (QLC) programming are provided. In one example, a controller of the storage system is configured to create codewords for lower, middle, and upper pages of data; program the codewords in the memory of the storage system using a triple-level cell programming operation; read the programming of the codewords for the lower, middle, and upper pages of data in the memory; create a codeword for a top page of data; and program the codeword in the memory.