Critical Path Sensitization Using Direct Scan Chain Loading
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Solution Overview
Problem
Existing methods for critical path sensitization in electronic systems, such as integrated circuits, result in increased area and power consumption, design complexity, and performance degradation due to the use of additional logic gates and inefficient scan chain configurations, leading to inaccurate sensitization of functionally valid paths.
Innovation Solution
A sensitizing circuit with a control circuit and scan chains is employed to accurately sensitize critical paths by directly configuring relevant scan chains with configuration datasets, bypassing decompressors and avoiding concatenation, thus reducing run and test time, and ensuring only functionally valid paths are sensitized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional logic gates are used for critical path sensitization, then sensitization accuracy is improved, but area and power consumption increase
Solution Approach 1:
The patent extracts and removes the decompressor component from the test configuration system. By directly configuring scan chains with test patterns without requiring decompression, the solution eliminates the area and power overhead associated with decompressors while maintaining sensitization accuracy through direct pattern application to scan chains.
Solution Approach 2:
The patent makes scan chains multi-functional by enabling them to serve both as test pattern storage and as direct configuration elements for critical path sensitization. This eliminates the need for separate decompressor logic, as the scan chains themselves perform the configuration function, thereby reducing overall circuit area and power consumption.
2Measurement precision
If additional logic gates are used for critical path sensitization, then sensitization accuracy is improved, but design complexity increases
Solution Approach 1:
The patent removes the decompressor from the test configuration architecture, simplifying the design by eliminating an entire component block. This extraction reduces design complexity while maintaining the ability to accurately sensitize critical paths through direct scan chain configuration with test patterns.
Solution Approach 2:
Instead of using a decompressor to expand compressed patterns into scan chain configurations, the patent inverts the approach by directly loading full test patterns into scan chains. This inversion eliminates the decompression step and associated complexity, achieving sensitization through a simpler direct configuration method.
3Reliability
If scan chains are concatenated for sensitization, then coverage is improved, but run and test time increase
Solution Approach 1:
The patent segments the test configuration process by allowing independent configuration of individual scan chains rather than requiring sequential concatenation. Each scan chain can be loaded and configured independently with its test pattern, enabling parallel operation and significantly reducing the total time required compared to sequential concatenation approaches.
Solution Approach 2:
The patent applies partial action by configuring only the necessary portions of scan chains required for critical path sensitization rather than concatenating all scan chains. This selective configuration achieves adequate coverage for critical paths while minimizing the time and resources required, avoiding the excessive action of full concatenation.
4Adaptability or versatility
If decompressors are used for scan chain configuration, then configuration flexibility is improved, but area and power consumption increase
Solution Approach 1:
The patent extracts and removes the decompressor component entirely from the system. By directly configuring scan chains with test patterns, the solution eliminates the power consumption associated with decompressor operation while maintaining configuration flexibility through direct pattern loading into scan chains.
Solution Approach 2:
The scan chains serve themselves by directly receiving and holding test patterns without requiring external decompression functionality. This self-service approach eliminates the need for decompressor circuits and their associated power consumption, while scan chains maintain their inherent flexibility in storing and providing test configurations.
Data Source
AI summary
An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.