Direct Sequence Detection Circuit for High-Speed Receivers
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Solution Overview
Problem
Existing high-speed receivers face challenges in accurately detecting sequences of symbols over communication channels due to inter-symbol interference (ISI), which often require high power consumption and large chip area, especially when using analog-to-digital converters (ADCs) for digital signal processing.
Innovation Solution
The proposed solution involves a sequence detection method that sets comparator thresholds based on different combinations of main, pre-cursor, and post-cursor components, allowing for direct analog-to-sequence detection without the need for ADCs, thereby reducing power consumption and chip area. This method generates a set of possible sequences based on the sampled voltage and selects the most likely sequence using previously detected symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog-to-digital converters (ADCs) are used for digital signal processing in high-speed receivers, then sequence detection accuracy can be improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the receiver architecture, replacing it with direct analog-to-sequence detection using comparator circuits. This eliminates the need for high-power ADCs while maintaining detection accuracy through direct comparison of sampled voltages with reference voltages corresponding to different symbol sequences.
Solution Approach 2:
The patent substitutes the electronic ADC-based digital signal processing system with a direct analog comparison system using comparator circuits. Instead of converting analog signals to digital through ADCs and then processing digitally, the system directly compares analog sampled voltages with analog reference voltages to determine symbol sequences, thereby eliminating ADC power consumption.
2Measurement precision
If analog-to-digital converters (ADCs) are used for digital signal processing in high-speed receivers, then sequence detection accuracy can be improved, but chip area increases significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the receiver architecture, replacing it with direct analog-to-sequence detection using comparator circuits. This eliminates the need for large-area ADCs while maintaining detection accuracy through direct comparison of sampled voltages with reference voltages.
Solution Approach 2:
The patent substitutes the electronic ADC-based digital signal processing system with a direct analog comparison system using comparator circuits. This substitution dramatically reduces chip area since comparator circuits occupy significantly less area than high-resolution ADCs while achieving the same sequence detection function.
3Device complexity
If traditional symbol-by-symbol detection is used, then device complexity is lower, but detection accuracy deteriorates due to inter-symbol interference (ISI)
Solution Approach 1:
The patent applies preliminary equalization before detection by pre-computing reference voltages that incorporate expected ISI effects. The reference voltages are generated based on anticipated pre-cursor and post-cursor interference patterns, allowing the comparator to directly identify the correct symbol sequence without requiring complex post-detection equalization algorithms.
Solution Approach 2:
The patent transitions from one-dimensional symbol-by-symbol detection to multi-dimensional sequence detection by comparing sampled voltages against reference voltages representing entire symbol sequences simultaneously. This dimensional shift allows the system to detect multiple symbols in parallel while inherently accounting for ISI between them, improving accuracy without increasing algorithmic complexity.
Data Source
AI summary
Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.