Direct Storage Buffer Architecture for Low-Latency Accelerator Access
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Solution Overview
Problem
Existing storage systems face inefficiencies in supporting direct storage functions, particularly when accelerators like GPUs offload tasks from CPUs, as they require using system buffer memory, leading to degraded system performance.
Innovation Solution
Implementing a storage device with a multi-port and multi-physical function structure that supports the Compute Express Link (CXL) protocol, allowing accelerators to directly access the storage device's internal buffer memory without relying on external system buffer memory, thereby optimizing data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerators access storage devices through external system buffer memories, then data access can be performed, but system performance is degraded due to increased latency and reduced processing speed
Solution Approach 1:
The patent extracts the buffer memory function from the external system and relocates it directly into the storage device. The storage device includes an internal buffer memory that can directly receive and hold data from accelerators, eliminating the need for external buffer memories and the associated data transfer overhead, thereby reducing latency and improving system performance
Solution Approach 2:
The patent introduces a buffer memory as an intermediary component within the storage device that mediates data transfer between accelerators and nonvolatile memory. This internal buffer acts as a staging area that allows accelerators to write data directly without waiting for nonvolatile memory operations, reducing processing delays and improving overall system productivity
2Adaptability or versatility
If storage devices use traditional single-port structures, then device complexity is low, but adaptability to support direct storage functions for multiple accelerators is limited
Solution Approach 1:
The patent implements a multi-port structure where the storage device can simultaneously support multiple accelerators through separate ports. Each port can independently handle direct storage operations with its own buffer memory allocation, allowing the storage device to serve multiple functions and multiple clients concurrently, thereby enhancing adaptability without requiring separate storage devices for each accelerator
Data Source
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AI summary
A storage device includes one or more ports that form an electrical connection with an external device, one or more physical functions including physical resources, and exposed through the one or more ports to communicate with the external device, a storage controller that controls an operation of the storage device, and communicates with the external device through the one or more ports and the one or more physical functions, nonvolatile memories controlled by the storage controller, and a first buffer memory controlled by the storage controller. When the storage device is accessed by the external device, the first buffer memory is used by the one or more ports and the one or more physical functions to temporarily store data for the external device.