Direct Testing of 3D Semiconductor Memory Structures
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Solution Overview
Problem
Current methods for testing and characterizing 3D semiconductor memory structures are inefficient, particularly in early stages of development, as they require complex peripheral circuitry and struggle to detect defects like opens and shorts in vertical NAND memory arrays, leading to increased costs and manufacturing iterations.
Innovation Solution
A direct tester that probes word lines, select lines, and channel pillars to detect electrical opens and shorts, eliminating the need for decoders or multiplexers, allowing for high-speed characterization of large populations of memory cells and accelerating process development by providing statistical data on defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods with peripheral circuitry are used, then memory structures can be tested, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the complex peripheral circuitry (decoders, multiplexers) from the testing system by implementing direct probing of memory cells through contact holes, achieving simplified testing architecture while maintaining defect detection capability
Solution Approach 2:
The patent introduces contact holes as intermediary structures that enable direct electrical access to memory cells, serving as a simple mediator between the testing apparatus and the memory array without requiring complex peripheral circuitry
2Measurement precision
If conventional testing methods are used, then memory structures can be characterized, but the measurement precision for detecting opens and shorts is insufficient
Solution Approach 1:
The patent replaces complex mechanical/electrical testing systems with direct electrical probing through contact holes, achieving high measurement precision for detecting opens and shorts by establishing direct electrical pathways to memory cells
3Ease of manufacture
If early phase testing is implemented, then manufacturing costs are reduced, but the testing methodology must be simplified
Solution Approach 1:
The patent implements preliminary testing action by enabling defect detection at early manufacturing stages through direct probing methodology, allowing identification and correction of issues before full fabrication completion, thereby reducing overall manufacturing costs while maintaining detection capability
Data Source
AI summary
Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.