Direct User-Level Interrupt Delivery Without Privilege Transitions
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Solution Overview
Problem
Existing systems incur significant latency due to multiple privilege level transitions when user-level applications interact with I/O devices, exceeding the operational latency of the I/O devices.
Innovation Solution
Implementing a user-level interrupt mechanism that delivers interrupts directly to user-level applications without privilege level transitions, using a user-level APIC and interrupt handler address data structure managed by the processor and operating system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are delivered through the OS kernel to user-level applications, then system stability and security are maintained through privilege level management, but significant latency is introduced due to multiple privilege level transitions
Solution Approach 1:
The interrupt delivery path is segmented into two separate mechanisms: kernel-mode interrupts for system-level operations and user-mode interrupts for application-level operations. This segmentation allows each mode to handle appropriate interrupts without requiring privilege level transitions, resolving the contradiction between maintaining system stability through proper privilege management and reducing latency by eliminating unnecessary mode switches.
Solution Approach 2:
An intermediary user-mode interrupt handler is introduced between the hardware interrupt controller and the application. This handler receives interrupts in user mode and processes them without requiring transitions to kernel mode, thereby maintaining system stability through the structured interrupt handling framework while eliminating the latency caused by privilege level transitions.
2Ease of operation
If traditional kernel-mode interrupt handling is used, then proper privilege level management and system security are ensured, but the operational latency exceeds that of the I/O devices themselves
Solution Approach 1:
The system is divided into kernel-mode and user-mode interrupt handling paths. I/O interrupts that can be safely handled at user level are routed through the user-mode interrupt handler, eliminating unnecessary privilege transitions and matching or exceeding I/O device operational speed, while kernel-mode handling remains available for operations requiring elevated privileges.
Solution Approach 2:
The system performs preliminary classification of interrupts to determine whether they can be handled in user mode or require kernel mode. By pre-configuring interrupt routing and establishing user-mode handlers in advance, the system prepares the appropriate handling path before the interrupt occurs, eliminating latency while maintaining security through proper privilege management.
3Reliability
If multiple privilege level transitions are performed for I/O operations, then system security and proper access control are maintained, but software latency significantly exceeds I/O device operational latency
Solution Approach 1:
Access control is segmented into two layers: kernel-mode access control for system-critical resources and user-mode access control for application-level I/O operations. This allows user-level applications to handle I/O interrupts with appropriate access control enforced at the user mode level, eliminating multiple privilege transitions while maintaining proper access control through the structured interrupt handling framework.
Data Source
AI summary
Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.