Direct-Contact Well Strap Structure for Lower Pick-Up Resistance
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Solution Overview
Problem
As semiconductor technology advances to smaller nodes, well straps in integrated circuits face increased well pick-up resistance and degraded latch-up performance, particularly in non-planar transistors, leading to inefficiencies and complexity in manufacturing.
Innovation Solution
The implementation of conductive plugs that extend fully through isolation layers to directly contact well regions without intervening semiconductor structures, reducing well pick-up resistance and improving latch-up performance, and allowing for efficient use of chip real estate by eliminating the need for anti-type source/drain masking steps and dummy regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional well strap structures are used in scaled-down IC nodes, then manufacturing complexity increases, but well pick-up resistance and latch-up performance degrade
Solution Approach 1:
The patent removes the anti-type source/drain masking step and dummy regions from the well strap structure, extracting the problematic elements that caused manufacturing complexity while maintaining the essential well strap functionality through direct conductive contact to the well region
Solution Approach 2:
Instead of using complex multi-layer conductive structures or indirect paths, the patent inverts the approach by using a simple direct conductive plug that extends through the isolation layer to contact the well region, simplifying the structure while improving reliability
2Productivity
If scaling down process is applied to increase production efficiency, then production efficiency increases, but well pick-up resistance increases and latch-up performance degrades
Solution Approach 1:
The patent changes the geometric parameters of the well strap structure by extending the conductive plug fully through the isolation layer to directly contact the well region, increasing the contact area and reducing resistance without requiring larger overall device dimensions, thus maintaining scalability
3Ease of manufacture
If conventional well strap structures with anti-type source/drain masking are used, then manufacturing process is established, but chip area is wasted and lithography complexity increases
Solution Approach 1:
The patent extracts and removes the anti-type source/drain masking step and dummy regions from the manufacturing process, eliminating the steps that consumed chip area and added lithography complexity while maintaining manufacturing feasibility through the simplified direct conductive plug structure
Solution Approach 2:
The conductive plug structure serves multiple functions: it provides the well strap connection, acts as the contact structure, and eliminates the need for separate anti-type masking and dummy regions, reducing overall chip area usage while simplifying the manufacturing process
Data Source
AI summary
An integrated circuit structure includes: a well region having a first conductivity type; a semiconductor structure extending away from the well region from a major surface of the well region, the semiconductor structure having the first conductivity type; a source/drain feature disposed on the semiconductor structure, the source/drain feature having a second conductivity type different from the first conductivity type; an isolation layer laterally surrounding at least a portion of the semiconductor structure; a dielectric layer disposed on the isolation layer, where at least a portion of the source/drain feature is disposed in the dielectric layer; and a conductive plug continuously extending through the dielectric layer and the isolation layer to physically contact the major surface of the well region, wherein the conductive plug is coupled to a power supply line to bias the well region.