Direct Write Interconnections for Low Inductance Semiconductor Packages
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Solution Overview
Problem
Existing methods for electrically connecting power semiconductor devices to external circuits, such as wirebonding and conventional power overlay packaging, increase inductance and production time and cost, and are not suitable for non-uniform die thicknesses.
Innovation Solution
A direct write process is employed to form a conformal dielectric layer with vias over semiconductor devices on a substrate, allowing for the formation of interconnect structures that extend through these vias to connect with device connection pads, reducing inductance and package profile while accommodating non-uniform die thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonding is used to connect power semiconductor devices to external circuits, then electrical connection is achieved, but inductance increases and package profile increases
Solution Approach 1:
The patent removes the wirebond component entirely from the packaging system. Instead of using separate wirebonds to connect devices to the substrate, the invention integrates the interconnection function directly into the substrate through conductive pathways formed in the dielectric layers, thereby eliminating the need for wirebonds and reducing package profile.
Solution Approach 2:
The patent merges the functions of the substrate, interconnect, and packaging structure into a single integrated substrate assembly. The conductive pathways are formed directly within the substrate's dielectric layers, combining what were previously separate components (wirebonds, substrate, and packaging) into one unified structure that reduces overall package height and inductance.
2Reliability
If conventional power overlay packaging is used, then electrical connection is achieved, but production time and cost increase
Solution Approach 1:
The patent performs the interconnection formation as a preliminary action during substrate manufacturing, before device assembly. Conductive pathways are pre-formed within the substrate's dielectric layers using standard semiconductor fabrication techniques, so that when devices are mounted, electrical connections are already in place, eliminating post-assembly interconnection steps and reducing production time.
Solution Approach 2:
The patent replaces mechanical wirebonding operations with automated semiconductor fabrication processes. Instead of using mechanical wirebonding equipment to create connections after assembly, the invention uses deposition and etching processes to form conductive pathways during substrate manufacturing, which are more automated and faster.
3Ease of manufacture
If conventional packaging methods are used, then standard packaging is achieved, but adaptability to non-uniform die thicknesses is poor
Solution Approach 1:
The patent applies local quality by allowing the dielectric layers to have varying thicknesses in different regions of the substrate. The conformal deposition process creates dielectric layers that adapt to the local topography beneath them, providing different dielectric thicknesses over areas with different device heights, thereby accommodating non-uniform die thicknesses while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a low-cost, thin, low-inductance package with improved performance compared to wirebonding and conventional packaging methods, capable of handling non-uniform die thicknesses and reducing production time and costs.
Implementation Method 1
depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application
Implementation Method 2
forming an interconnect structure on the dielectric layer that is electrically coupled to the at least one connection pad of the at least one device, the interconnect structure extending through the vias in the dielectric layer
Data Source
AI summary
A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads.