Directed Graph Recursion Check via Minimal Subgraph Topological Sort
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Solution Overview
Problem
Current algorithms for recursion check and low-level code generation in directed graphs, especially in large and complex Bill of Materials (BOM) systems, are time-consuming and lead to system performance issues due to the need for frequent topological reordering and recalculating codes when graph structures change.
Innovation Solution
A method that performs a topological sort in linear time on a minimum set of nodes and arcs potentially violating the low-level code rule, recalculating only conflicting codes and avoiding unnecessary reordering of the entire graph, by identifying direct or indirect successors of new arcs that violate the rule and adjusting their codes accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional algorithms are used for recursion check and low-level code generation in large and complex BOM systems, then complete graph reordering and code recalculation ensure consistency, but execution time increases significantly and system performance deteriorates
Solution Approach 1:
The patent segments the graph processing into two parts: (1) identifies and processes only the minimal subset of nodes and arcs affected by the new edge, and (2) leaves the rest of the graph unchanged. This is achieved by performing topological sort only on the minimal subgraph containing the new edge and its descendants, rather than reordering the entire graph, thus reducing execution time while maintaining code consistency.
Solution Approach 2:
The patent applies local quality by making the code recalculation process localized to only those parts of the graph that are actually affected by the change. Specifically, it recalculates low-level codes only for nodes in the minimal subgraph that contains the new edge and its descendants, rather than uniformly recalculating codes for all nodes in the graph, thereby optimizing performance.
2Reliability
If frequent topological reordering is performed to maintain code consistency after graph changes, then code consistency is maintained, but system performance and processing speed deteriorate
Solution Approach 1:
The patent applies partial action by performing topological reordering only to the extent necessary - specifically, only on the minimal subgraph containing the new edge and its descendants - rather than performing complete graph reordering. This partial reordering maintains code consistency for affected nodes while avoiding unnecessary processing of unrelated parts of the graph, thus improving processing speed.
3Reliability
If complete graph reordering is performed to handle added vertices and edges, then code consistency is maintained, but the complexity and time consumption of the operation increases
Solution Approach 1:
The patent extracts and isolates the minimal subgraph containing the new edge and its descendants from the larger graph structure. By separating this affected subgraph from the rest of the graph, the algorithm can apply topological reordering only to this extracted subset, reducing the computational complexity from O(V+E) for the entire graph to O(V'+E') for the minimal subgraph, where V' and E' are significantly smaller than V and E.
Data Source
AI summary
A method and a system for fast recursion check and low-level code generation for directed graph. In a directed graph each vertex is connected to at least one other vertex with a directed edge to form an ordered pair of a source vertex and a target vertex. Low-level codes are assigned to the vertices of the directed graph, where for each ordered pair the low-level code of the target vertex is bigger than the low-level code of the source vertex. A new edge is added to connect a first vertex and a second vertex of the graph, where the first vertex is the source vertex and the second vertex is the target vertex of the new ordered pair. The low-level code of the target vertex of the new ordered pair is not bigger than the low-level code of the source vertex. For the new ordered pair and all ordered pairs that descend from the new ordered pair, the low-level codes of the target nodes are changed to values bigger than the low-level codes of the corresponding source vertices, when necessary.