Directed Interrupt Virtualization via Bus Attachment Device
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Solution Overview
Problem
In multiprocessor computer systems, efficiently routing interrupt signals from bus-connected modules to the appropriate processor is challenging, especially when communicating with guest operating systems on virtual machines, as the mapping between logical and virtual processor IDs is dynamic and not static, leading to inefficiencies in interrupt handling.
Innovation Solution
Implementing a directed interrupt mechanism using Message Signaled Interrupts (MSI) and MSI-X, where the bus attachment device translates interrupt target IDs to logical processor IDs, allowing direct addressing of the target processor, thereby avoiding broadcast and minimizing cache traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcasting is used to forward interrupt signals to multiple processors, then the interrupt signal can reach a suitable processor, but the efficiency is reduced due to unsuccessful broadcasts and cache traffic
Solution Approach 1:
The patent introduces a hypervisor as an intermediary layer between the interrupt controller and guest operating systems. The hypervisor intercepts interrupt signals, determines the appropriate virtual processor using a mapping table, and forwards them directly. This mediator resolves the contradiction by enabling reliable interrupt delivery through proper routing while avoiding inefficient broadcast mechanisms.
Solution Approach 2:
The patent changes the routing parameter from broadcast addressing to directed addressing based on virtual processor ID mappings. By maintaining and querying a mapping table that associates interrupt sources with specific virtual processors, the system transforms the interrupt delivery mechanism from a blind broadcast approach to a targeted delivery approach, improving efficiency while maintaining reliability.
2Adaptability or versatility
If the mapping between logical processor IDs and virtual processor IDs is dynamic, then the system is flexible and adaptable, but interrupt routing becomes inefficient because the mapping changes without guest OS knowledge
Solution Approach 1:
The hypervisor serves as a mediator that manages the dynamic mapping between logical and virtual processor IDs. It maintains an updated mapping table and intercepts interrupt signals to perform translation and routing. This intermediary approach allows the mapping to remain dynamic and flexible while the hypervisor handles the complexity of tracking and applying these changes, preventing the guest OS from needing to know about mapping changes.
Solution Approach 2:
The system implements feedback mechanisms where the hypervisor continuously monitors processor assignments and updates the interrupt routing mapping accordingly. When processor assignments change, the hypervisor receives feedback about the new configuration, updates its internal mapping tables, and ensures subsequent interrupt routing reflects these changes. This feedback loop maintains adaptability while managing routing complexity centrally.
3Reliability
If broadcast interrupt forwarding is used, then all processors receive the interrupt signal, but cache traffic increases and performance decreases
Solution Approach 1:
The hypervisor acts as an intermediary that intercepts interrupt signals before they are broadcast to all processors. It queries the mapping table to determine the specific virtual processor that should handle the interrupt and forwards the signal only to that processor. This eliminates unnecessary cache traffic to other processors while ensuring the interrupt reaches the correct target, resolving the contradiction between reliable delivery and energy efficiency.
Solution Approach 2:
The patent changes the interrupt delivery parameter from broadcast mode to unicast mode based on virtual processor ID mappings. By maintaining a mapping table that identifies the specific target processor for each interrupt source, the system transforms the delivery mechanism to send interrupts only to the appropriate processor, reducing cache traffic and energy consumption while maintaining reliable delivery.
Data Source
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AI summary
The invention relates to a method for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.