Directed Memory Scrubbing for ECC Code Word Error Recovery
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Solution Overview
Problem
Conventional memory devices with error correction and scrub (ECS) operations perform scrubbing at fixed intervals, leading to potential accumulation of multiple errors in memory cells beyond the correction capacity of error-correction codes, increasing the likelihood of aliasing and data loss.
Innovation Solution
Implementing a directed ECS procedure that prioritizes scrubbing memory cells with detected errors by storing error addresses and performing internal read-modify-write cycles on these cells, notified by the memory device to the host, and updating the scrubbing order based on error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECS procedures are performed at fixed intervals, then the operation schedule is simple and predictable, but errors may accumulate multiple bit errors exceeding ECC correction capacity before being addressed
Solution Approach 1:
The memory device monitors its own error status through ECC circuits and provides feedback information about detected errors. This feedback mechanism enables the memory device to identify which code words contain errors and prioritize them for ECS procedures, transforming the fixed-interval approach into a dynamic, error-driven schedule that addresses critical errors immediately while maintaining simple operation for the host system.
Solution Approach 2:
The memory device performs self-diagnosis and self-management by autonomously identifying errors in its own storage cells and initiating ECS procedures for affected code words without requiring host intervention. The memory device maintains an error status register that tracks which code words need scrubbing and automatically schedules ECS operations based on this internal state, enabling the system to service its own errors proactively.
2Reliability
If ECS procedures are performed immediately upon error detection, then data integrity is improved, but additional operational overhead and complexity are introduced
Solution Approach 1:
The memory device autonomously manages the entire ECS process including error detection, prioritization, and execution without requiring complex host controller logic. The memory device maintains internal data structures (error status register) and autonomously schedules ECS procedures, keeping the complexity contained within the memory device itself while presenting a simple interface to the host system.
Solution Approach 2:
The patent introduces an intermediary error status register that mediates between error detection and ECS execution. This register stores the addresses of code words requiring scrubbing and serves as a buffer that decouples the error detection process from the ECS execution process, allowing the system to manage complex error handling operations without requiring complex real-time coordination between the host and memory device.
Data Source
AI summary
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.