Directed Page Table Entry Invalidation for Multi-Core TLBs
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Solution Overview
Problem
In multi-core processors, the broadcast of page table entry invalidation messages across all cores creates communication bottlenecks and performance degradation due to unnecessary traffic on system buses and mesh networks, especially as the number of cores increases.
Innovation Solution
Implementing directed page table entry invalidation by sending targeted messages to specific sets of cores assigned to execute instructions for a virtual machine, reducing unnecessary communication traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcast invalidation messages are sent to all cores, then page table entry invalidation reliability is ensured, but communication traffic and system bus congestion increase
Solution Approach 1:
The patent segments the invalidation message transmission by dividing all cores into multiple groups. Instead of broadcasting to every core individually, the message is sent to a representative core of each group, which then distributes it to other cores in its group. This segmentation reduces the total number of message transmissions while ensuring all cores receive the invalidation notice.
Solution Approach 2:
The patent introduces intermediary cores (representative cores) that act as mediators between the message source and other cores in the system. These intermediary cores receive the invalidation message and forward it to their respective groups, reducing the direct communication burden on the system bus and eliminating the need for every core to send individual acknowledgments.
2Stability of the object's composition
If broadcast invalidation messages are sent to all cores, then consistent address translation is maintained, but system performance degrades due to communication bottlenecks
Solution Approach 1:
By segmenting cores into groups with representative cores, the patent maintains address translation consistency across all cores while reducing the communication overhead. Each representative core ensures its group maintains consistency, and the segmented approach prevents system-wide bottlenecks that would degrade overall performance.
Solution Approach 2:
The patent applies partial action by sending invalidation messages only to representative cores of each group rather than to every core individually. This partial approach is sufficient to maintain system-wide consistency because each representative core propagates the message to its group members, achieving the same consistency goal with reduced communication activity and improved performance.
3Loss of information
If individual acknowledgments are received from every core, then message delivery confirmation is ensured, but communication overhead and processing time increase
Solution Approach 1:
The patent merges the acknowledgment process by having representative cores collect acknowledgments from their respective group members and then send a single consolidated acknowledgment to the message source. This combining of multiple individual acknowledgments into one reduces the total number of communication transactions and decreases the time required to confirm message delivery system-wide.
Solution Approach 2:
Representative cores serve as intermediaries that handle the acknowledgment collection and consolidation process. They receive individual acknowledgments from group members, verify message delivery within their group, and then provide a unified confirmation to the original message sender, reducing the communication overhead on the system bus.
Data Source
AI summary
A first core in a processor-based system may obtain information that identifies cores in a first set of cores, where the information also indicates that at least one core of the first set of cores is assigned to execute instructions for a first VM. The first core sends a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM in the core TLBs of the first set of cores. A message to invalidate copies of a page table entry may be sent in advance of modifying the page table entry of the first VM in a memory system. Sending a message directed to the first set of cores to invalidate copies of page table entries in the first set of cores, instead of an invalidation message broadcast to all cores in the processor-based system, reduces communication traffic.