Direction-Based IMC Processor Macros for MAC Efficiency
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Solution Overview
Problem
In memory computing (IMC) processors face inefficiencies in performing multiply and accumulate (MAC) operations due to the mismatch between data write direction and operation direction in traditional architectures, leading to increased processing time and power consumption.
Innovation Solution
The implementation of a static random access memory (SRAM) IMC device with type 1 and type 2 IMC macros, where the write direction of data is the same as the operation direction in type 1 macros and different in type 2 macros, allowing for efficient MAC operations between input feature maps and weights, with a shift accumulator performing partial sum operations and accumulating results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional IMC processor architecture is used, then MAC operations can be performed, but data movement overhead and processing time increase due to mismatch between write direction and operation direction
Solution Approach 1:
The IMC processor is segmented into two distinct types of IMC macros: type 1 macros where write direction matches operation direction, and type 2 macros where write direction differs from operation direction. This segmentation allows each macro type to be optimized for specific dataflow patterns, eliminating the need for costly direction mismatches in all macros and thereby reducing overall processing time.
Solution Approach 2:
The patent inverts the traditional single-architecture approach by creating type 2 IMC macros that deliberately operate with write direction different from operation direction. This inversion is compensated by the complementary type 1 macros, allowing the system to handle diverse dataflow requirements efficiently without uniform architectural constraints.
2Productivity
If traditional IMC processor architecture is used, then MAC operations can be performed, but energy consumption increases due to increased data movement
Solution Approach 1:
By segmenting the IMC processor into type 1 and type 2 macros, each optimized for specific write-operation direction relationships, the system minimizes unnecessary data movement. Type 1 macros handle cases where write and operation directions align, while type 2 macros handle mismatched directions, collectively reducing the total energy required for data movement during MAC operations.
3Device complexity
If single type of IMC macro is used, then device complexity is reduced, but adaptability to different dataflow patterns is limited
Solution Approach 1:
The processor is divided into two macro types with distinct directional characteristics. Type 1 macros are optimized for matched write-operation directions, while type 2 macros handle mismatched directions. This segmentation provides adaptability to various dataflow patterns without requiring a completely different architecture for each case, balancing complexity and versatility.
Solution Approach 2:
Both type 1 and type 2 IMC macros are designed to perform MAC operations, but with different directional optimizations. This multi-functionality allows the processor to adapt to various dataflow patterns using the same basic MAC operation framework, enhancing versatility while maintaining relatively simple macro structures.
Data Source
AI summary
Disclosed is an in memory computing (IMC) processor. An in memory computing (IMC) processor includes a static random access memory (SRAM) IMC device including type 1 IMC macros in which a direction of writing data therein is the same as an operation direction of performing a multiply and accumulate (MAC) operation in the type 1 IMC macros, and type 2 IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros, and the SRAM IMC device is configured to use the type 1 IMC macros and the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight, and a shift accumulator configured to perform a shift operation on an output of the SRAM IMC device and accumulate a result of the shift operation.