Directional Blocking Layer for High-Aspect-Ratio Memory Hole Taper
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Solution Overview
Problem
High aspect ratios in semiconductor device stacks lead to increased profile taper and cell voltage variation, making it difficult to etch thicker stacks effectively, particularly in 3D NAND devices.
Innovation Solution
A method involving directional deposition of a blocking layer, such as carbon, is applied only to the upper portion of memory holes or vias, allowing for selective etching of the lower portion without affecting the upper portion, thereby reducing taper and enhancing uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional layers are stacked to increase device density, then the number of structures per unit area increases, but the aspect ratio of etched openings increases leading to profile taper
Solution Approach 1:
A blocking layer is deposited on the upper portion of the opening before the etching process. This preliminary action protects the upper portion from etching, allowing the lower portion to be etched with a wider opening width, thereby preventing profile taper while enabling the stacking of additional layers for increased device density.
2Stability of the object's composition
If conventional isotropic deposition is used, then material is deposited uniformly in all directions, but this results in blocking layer formation on both upper and lower portions of the opening
Solution Approach 1:
The deposition process uses asymmetric oblique angles (e.g., +45 degrees and -45 degrees) instead of isotropic normal incidence. This asymmetry causes the blocking layer to be deposited preferentially on the upper portion of the opening sidewalls while avoiding the lower portion, achieving selective blocking layer formation that enables precise control over etching profiles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform memory hole dimensions and reduced taper, improving etching efficiency and cell voltage consistency without impacting the upper portion of the memory holes.
Implementation Method 1
forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures
Data Source
AI summary
Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.