Directional Etching for Semiconductor Interlayer Dielectric Patterning
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Solution Overview
Problem
As semiconductor devices continue to shrink, traditional photolithography equipment struggles to maintain the required spacing between elements, approaching the limits of its capabilities, making it difficult to manufacture devices with increasingly smaller dimensions and higher density.
Innovation Solution
A directional etching process is employed, using a combination of photolithographic patterning and plasma etching to expand patterned openings in the IMD layer, allowing for the formation of conductive lines with reduced separation distances and increased density, by etching sidewalls at a shallow angle to achieve smaller pitch and line cut distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography equipment is used to manufacture semiconductor devices, then manufacturing process is simpler, but the spacing between elements cannot be reduced below a certain pitch limit
Solution Approach 1:
The manufacturing process is divided into multiple stages: first forming initial openings with photolithography, then performing directional etching to expand them, and finally forming conductive lines. This segmentation allows each stage to optimize for its specific function, achieving smaller pitch than traditional single-step photolithography
Solution Approach 2:
The patent transitions from two-dimensional photolithographic patterning to three-dimensional directional etching by etching sidewalls at shallow angles. This adds a vertical dimension to the patterning process, enabling reduced horizontal spacing between features
2Manufacturing precision
If photolithography equipment is pushed to its theoretical limits to achieve smaller pitch, then element spacing is reduced, but manufacturing reliability and process window deteriorate
Solution Approach 1:
The patent introduces directional etching as an intermediary process between photolithography and final conductor formation. This mediator step expands the initial patterns with better process control and larger process windows, reducing the stress on photolithography equipment
Solution Approach 2:
The photolithography step performs preliminary patterning to define initial opening locations, but the critical dimension control is achieved in the subsequent directional etching step. This preliminary action separates the location definition from the dimension control functions
3Manufacturing precision
If directional etching is used to expand patterned openings and reduce separation distances, then pattern density increases, but process complexity increases
Solution Approach 1:
The directional etching process changes key parameters including etch direction (shallow angle), etch selectivity (using multiple mask layers), and process temperature. These parameter changes enable precise control of separation distances while managing the increased process complexity through systematic optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of conductive lines with reduced end-to-end separation distances, increasing pattern density and reducing semiconductor device size, while maintaining process efficiency and reducing line width roughness.
Implementation Method 1
performing a plasma etching process that etches exposed sidewalls of the patterned second mask layer
Implementation Method 2
accelerating ions from the plasma toward the substrate in the ion beam direction
Data Source
AI summary
A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.