Directional Link Credit Pools for SoC Interconnect Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-core chip interconnect architectures face inefficiencies due to synchronized credit management across TX ports, leading to suboptimal resource utilization and potential head-of-line blocking under bursty traffic conditions.
Innovation Solution
Implementing directional link (DL) credit pools, where each TX port has an independent credit pool, allowing for asynchronous credit management and enabling continuous transmission across all directions even when out of credits in one direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synchronized credit management is used across TX ports, then system simplicity is maintained, but peak bandwidth utilization deteriorates due to head-of-line blocking
Solution Approach 1:
The patent segments the unified credit pool into multiple directional link credit pools, with each pool associated with a specific TX port. This segmentation allows independent credit management for each direction, preventing head-of-line blocking where one direction's credit exhaustion blocks other directions. The segmented structure maintains overall system manageability while enabling parallel credit operations across different ports.
Solution Approach 2:
The patent introduces dynamic credit allocation where each TX port has its own credit pool that can be independently incremented and decremented based on real-time link status and traffic conditions. This dynamic approach allows the system to adapt to bursty traffic patterns in different directions simultaneously, maximizing peak bandwidth utilization without requiring a complex static structure.
2Productivity
If independent credit pools are implemented for each TX port, then resource allocation improves and head-of-line blocking is delayed, but device complexity increases
Solution Approach 1:
The patent applies local quality by associating each credit pool with a specific TX port and direction, giving each local component its own dedicated resources. This local quality ensures that credit availability in one direction does not affect other directions, improving overall resource utilization. The localized management keeps complexity contained at each port rather than requiring global coordination.
Solution Approach 2:
Each TX port autonomously manages its own credit pool through self-service mechanisms. The TX port logic independently increments credits when data is received and decrements credits when transmitting, without requiring centralized credit allocation. This self-service approach improves resource utilization while minimizing the complexity of inter-component coordination.
3Device complexity
If credits are managed synchronously across all TX ports, then coordination overhead is reduced, but transmission continuity deteriorates under bursty traffic conditions
Solution Approach 1:
The patent transitions from synchronous to asynchronous credit management, where each TX port operates independently based on its own credit pool status. This dynamic approach allows continuous transmission in directions with available credits even when other directions are temporarily blocked, maintaining transmission continuity under bursty traffic conditions while keeping coordination mechanisms simple.
Solution Approach 2:
By implementing independent credit pools, the patent ensures that useful transmission action continues in all directions that have available credits, rather than pausing all transmissions when any single direction exhausts its credits. This continuity is achieved through the asynchronous operation of each port's credit management, allowing parallel transmission streams to proceed independently.
Data Source
AI summary
A circuit and corresponding method employ directional link (DL) credit pools. The circuit comprises the DL credit pools and transmit (TX) port logic. The DL credit pools are associated with neighboring node (NBN) TX ports of a NBN on a chip. The NBN is coupled to a node on the chip via the circuit. The node includes the circuit. The TX port logic admits a received packet to the circuit based on routing information in the received packet and produces a TX packet by updating the routing information, in the received packet admitted, to indicate a NBN TX port of the NBN TX ports. The TX port logic transmits the TX packet produced to the NBN based on a DL credit pool of the DL credit pools that is associated with the NBN TX port indicated. Use of the DL credit pool mitigates head-of-line blocking under bursty traffic conditions.