Directory Cache Entry Segmentation for Coherency Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Directory caches in large multiple processor computing systems face limitations in the number of bits available for share vectors due to limited directory cache entry size and overhead usage, restricting the resolution and efficiency of cache coherency operations.
Innovation Solution
The method involves using two directory entries per memory line when it is stored in more than M caches, where the first entry stores basic information and the second entry stores additional details such as a share vector or address pointers, allowing for increased bit allocation without expanding the cache size, thereby enhancing resolution without reducing capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more bits are allotted to the share vector to increase resolution, then the cache coherency operation efficiency is improved, but the directory cache entry size is exceeded and capacity is reduced
Solution Approach 1:
The directory cache entry is divided into multiple fields: a first field for basic information (valid bit, dirty bit, share count) and a second field for additional information (share vector with more bits). This segmentation allows the share vector to have higher resolution without exceeding the total entry size constraint, as the first field handles basic coherency tracking while the second field provides detailed cache identification when needed.
2Measurement precision
If more bits are used for share vector to identify precise cache identities, then the cache coherency notification accuracy is improved, but the number of available bits for share vector is reduced due to overhead requirements
Solution Approach 1:
The directory cache entry is segmented into a first field containing essential overhead bits (valid bit, dirty bit, share count) and a second field containing the share vector. By separating these functions, the share vector can allocate more bits for precise cache identity identification without being constrained by the total entry size, as the first field absorbs the necessary overhead requirements.
Solution Approach 2:
Different parts of the directory cache entry have different functional requirements. The first field uses minimal bits for basic state tracking, while the second field (share vector) uses additional bits for precise cache identification. This local quality differentiation allows optimized bit allocation where each field receives the appropriate amount of bits for its specific purpose.
3Device complexity
If a single directory entry is used for all memory lines, then the device complexity is reduced, but the directory information storage capacity is limited
Solution Approach 1:
The directory cache entry is segmented into multiple fields that can be independently utilized. The first field stores basic information for all memory lines, while the second field stores additional share vector information only when needed (when more than M caches hold a copy). This segmentation enables the system to maintain simple single-entry structure for basic cases while expanding storage capacity for complex sharing scenarios without increasing overall structural complexity.
Data Source
AI summary
A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.