System Directory Capacity Scaling for Core Power State Transitions
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Solution Overview
Problem
The challenge of managing power consumption in multicore systems on a chip (SoC) is significant due to increased scale, including costs associated with supporting more DRAM channels, higher Thermal Design Points, and power consumption of CPU cores, particularly when not fully utilized, leading to idle cores that contribute to unnecessary energy usage.
Innovation Solution
Implementing dynamic power management to power gate idle core complexes in multicore SoCs, adjusting compute power, and modifying system directory capacity based on cache availability to match application parameters, thereby reducing power consumption and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system directory capacity is increased to track more cache lines, then data coherence and reliability are improved, but power consumption and device area increase
Solution Approach 1:
The system directory capacity is made dynamic rather than static. The directory controller receives notifications about core complex power state transitions and adjusts the tracked cache line capacity accordingly. When core complexes are powered off, the system directory reduces its tracking capacity for those cores, thereby reducing power consumption while maintaining data coherence for active cores.
Solution Approach 2:
The system directory changes its operational parameters based on the power state of core complexes. By receiving power state transition notifications, the directory controller modifies the number of cache lines tracked in the system directory, adapting the directory capacity parameter to match the current operational requirements and minimize energy usage.
2Reliability
If the system directory capacity is increased to track more cache lines, then data coherence is maintained, but device area and manufacturing cost increase
Solution Approach 1:
The system directory capacity is dynamically adjusted based on the number of active core complexes. The directory controller receives power state notifications and modifies the tracked cache line capacity accordingly, allowing the directory structure to scale its area requirements with actual usage rather than provisioning for maximum possible cores.
Solution Approach 2:
The system directory modifies its structural parameters by changing the number of tracked cache lines based on core complex power states. This parameter adjustment allows the directory to maintain appropriate data coherence tracking while reducing the physical area required in the semiconductor device.
3Productivity
If all core complexes are kept active to maintain full system capacity, then productivity is improved, but power consumption increases significantly
Solution Approach 1:
The system divides core complexes into active and powered-off segments based on workload requirements. The directory controller segments the system directory tracking capacity accordingly, maintaining full productivity for active cores while allowing idle cores to be powered off, thus reducing overall power consumption without sacrificing available system capacity when needed.
Solution Approach 2:
The system directory serves multiple functions: it maintains data coherence for active core complexes and dynamically adapts its capacity to support power state transitions. This multi-functionality allows the same directory structure to support both full productivity when all cores are active and energy-saving modes when some cores are powered off.
Data Source
AI summary
A system includes a core complex with multiple processor cores and multiple caches. The system also includes system directories that track cache residency in the caches of the core complex. Based at least in part on a power state transition of the core complex a system directory can adjust its capacity to track the cache residency.