Directory Controller Simulates Removed Nodes for Cache Coherence
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Solution Overview
Problem
In large-scale shared-memory multi-processor computer systems, removing a node without rebooting is challenging due to cache coherence protocols that assume all nodes are present, leading to errors and potential corruption of data.
Innovation Solution
Modifying cache coherence protocols to include a test for removed nodes, allowing simulation of the missing node's existence to maintain system integrity and prevent hardware or software failures, enabling 'hot swapping' of nodes without rebooting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence protocols are executed assuming all nodes are present, then data consistency is maintained, but node removal causes hardware or software errors
Solution Approach 1:
The patent introduces a directory controller as an intermediary between processors and memory that manages cache coherence. The directory controller tracks which nodes have cached copies of memory lines and coordinates invalidation messages. When a node is removed, the directory controller identifies the removed node and simulates its response, preventing errors while maintaining data consistency across remaining nodes.
Solution Approach 2:
The patent creates a simulated response from the removed node by having the directory controller generate fake acknowledgment messages that mimic what the removed node would have sent. This copying of the removed node's expected behavior allows the cache coherence protocol to complete successfully without actual communication with the absent node, preventing hardware or software errors.
2Reliability
If the system reboots to remove a node, then system stability is maintained, but ongoing computations are interrupted
Solution Approach 1:
The patent implements preliminary tracking of node presence status in the directory controller before removal occurs. When a node is marked for removal, the directory controller proactively identifies all cached memory lines associated with that node and initiates invalidation procedures in advance. This preliminary action ensures that when the node is actually removed, no coherence errors occur, allowing hot swapping without reboot while maintaining computation continuity.
3Reliability
If cache invalidation messages are sent to removed nodes, then coherence protocol completeness is maintained, but communication errors occur
Solution Approach 1:
The directory controller acts as an intermediary that intercepts cache invalidation messages destined for removed nodes. Instead of allowing these messages to be sent and fail, the directory controller identifies that the target node is removed and generates a simulated response locally, preventing communication errors while maintaining the appearance of protocol completeness.
Solution Approach 2:
The patent converts the potentially harmful situation of sending messages to removed nodes into a benefit by having the directory controller simulate the removed node's responses. This simulation prevents communication errors while maintaining protocol integrity, turning what would be a harmful error condition into a successful coherence maintenance operation.
Data Source
AI summary
A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.