Directory Descriptor Cache for Multi-Core Coherence
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Solution Overview
Problem
Current cache coherence schemes, particularly bus snooping and coherence directory schemes, face scalability issues in multi-core microprocessor systems with a large number of cores, leading to performance degradation due to high directory access frequencies.
Innovation Solution
Implementing a directory descriptor cache (DDC) for each memory controller to store cached copies of directory descriptors, reducing the need for frequent accesses to main memory and enabling efficient directory-based cache coherence across multiple processor cores, with updates propagated through a common bus or metadescriptor for maintaining cache coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bus snooping cache coherence schemes are used, then cache coherence is maintained, but the interconnect does not scale well for large number of cores
Solution Approach 1:
The patent segments the monolithic directory into distributed directory structures across multiple memory controllers or memory domains. Each memory controller maintains a portion of the directory, allowing the system to scale to more cores without requiring a single complex global interconnect. This segmentation enables independent management of cache coherence within each segment while reducing overall interconnect burden.
2Adaptability or versatility
If coherence directory schemes are used, then scalability to large number of cores is improved, but directory access frequency increases leading to performance degradation
Solution Approach 1:
The patent implements directory descriptor caches that pre-load and cache directory descriptor information before it is needed for coherence operations. By anticipating future directory access needs and preparing the data in advance in the descriptor caches, the system reduces the frequency and latency of actual directory accesses to main memory, thereby preventing performance degradation despite high directory access frequencies in scalable multi-core systems.
Solution Approach 2:
The patent introduces directory descriptor caches as intermediary structures between the caches and the main memory directory. These descriptor caches store metadata about cache lines including validity bits, ownership information, and other coherence-relevant data. This intermediary layer allows most coherence operations to be resolved without accessing main memory, significantly reducing directory access frequency and improving performance while maintaining scalability.
3Reliability
If directory descriptors are stored in main memory, then cache coherence is maintained, but frequent accesses to main memory reduce performance
Solution Approach 1:
The patent implements a nested cache hierarchy where directory descriptor caches are embedded within or closely coupled to the memory controller, which itself is connected to main memory. This nested structure allows the system to maintain directory information locally in the descriptor caches while preserving the ability to access main memory when necessary. The nested arrangement reduces access latency by providing multiple levels of caching, with the innermost level (descriptor cache) handling the majority of coherence operations without requiring main memory access.
Data Source
AI summary
Techniques are generally described for methods, systems, data processing devices and computer readable media related to multi-core parallel processing directory-based cache coherence. Example systems may include one multi-core processor or multiple multi-core processors. An example multi-core processor includes a plurality of processor cores, each of the processor cores having a respective cache. The system may further include a main memory coupled to each multi-core processor. A directory descriptor cache may be associated with the plurality of the processor cores, where the directory descriptor cache may be configured to store a plurality of directory descriptors. Each of the directory descriptors may provide an indication of the cache sharing status of a respective cache-line-sized row of the main memory.