Directory-Ordered Release Consistency Without Store Acknowledgments
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Solution Overview
Problem
The existing source ordering method for release consistency in computing systems with multiple processing units results in significant communication latency, increased interconnect traffic, and energy consumption due to repeated acknowledgement messages between the source processor and cache directory.
Innovation Solution
Implement directory ordering by using epoch numbers, store counters, and notification counters to directly order stores at the destination component (cache directory), eliminating the need for store acknowledgments and reducing the number of transmitted messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source ordering is used to ensure release consistency, then memory consistency is maintained, but communication latency increases due to repeated acknowledgement messages
Solution Approach 1:
The patent inverts the traditional source ordering approach by moving the ordering logic from the source processor to the destination cache directory. Instead of the source processor tracking and waiting for acknowledgments from each cache, the cache directory autonomously tracks store counters and manages ordering, eliminating the need for repeated acknowledgment messages and reducing communication latency while maintaining memory consistency.
Solution Approach 2:
The cache directory performs self-service by autonomously managing store counters and tracking the completion of store operations without requiring continuous communication with the source processor. The directory independently determines when stores are complete and manages the ordering of memory operations, reducing the communication overhead that would otherwise be required for the source processor to track and verify store completion.
2Reliability
If source ordering with repeated acknowledgements is used, then release consistency is achieved, but interconnect traffic increases
Solution Approach 1:
The patent extracts the acknowledgment messaging from the release consistency mechanism. By having the cache directory autonomously track store counters and manage ordering internally, the system removes the need for repeated acknowledgment messages to traverse the interconnect, significantly reducing interconnect traffic while maintaining release consistency through the directory's internal counter management.
3Reliability
If source ordering with frequent acknowledgements is used, then memory ordering is ensured, but energy consumption increases
Solution Approach 1:
The cache directory performs self-service by autonomously managing store counters and tracking store completion without requiring continuous communication with the source processor. This self-managed approach reduces the number of message transmissions across the interconnect, thereby reducing energy consumption while maintaining memory ordering guarantees through the directory's internal tracking mechanisms.
4Reliability
If source ordering is used, then release consistency is maintained, but device complexity increases due to acknowledgment tracking
Solution Approach 1:
The patent inverts the complexity location by moving the tracking and management logic from the source processor to the destination cache directory. The source processor is simplified to only issue store operations, while the cache directory assumes the complexity of tracking store counters and managing ordering. This inversion reduces source processor complexity and centralizes the ordering management where it can be more efficiently handled.
Data Source
AI summary
Various embodiments include techniques for inter-processor communication. The techniques include generating a relaxed store message that comprises a first epoch number, incrementing a first counter associated with the first epoch number, and transmitting the relaxed store message to a first directory included in a cache.