Directory Recovery via Address Segmentation for Uncorrectable Error Handling
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Solution Overview
Problem
Modern computer systems with cache coherent processing units face significant challenges due to the exponential growth of directory size and logic gate delays caused by full address storage and transmission, leading to performance degradation and increased manufacturing costs, especially when uncorrectable errors occur, which typically result in system directory disablement.
Innovation Solution
The system separates cache coherence functions into multiple distinct units, including Agent Interface Units, Coherence Controller Units, and Memory Interface Units, communicating through a transport network, and employs error detection to recover from uncorrectable errors by generating lists of possible affected addresses for invalidation, thereby preventing system-wide performance drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full addresses are stored in directory entries and cache tags, then address tracking accuracy is improved, but silicon area consumption increases significantly
Solution Approach 1:
The patent segments the full address into multiple fields including index field, tag field, and offset field. The directory entry stores only the index field while cache tags store the tag field, allowing address tracking without storing complete addresses in both structures simultaneously, thereby reducing silicon area while maintaining tracking accuracy.
Solution Approach 2:
The patent introduces a new dimension by adding the index field as a separate component that can be used for directory indexing without requiring the full address to be stored in the directory entry. This dimensional separation allows efficient address tracking with reduced storage requirements.
2Loss of information
If full addresses are transmitted between processing units and memory, then address information completeness is improved, but wire count and transmission complexity increase
Solution Approach 1:
The address transmission is segmented into different components sent through different pathways. The index field is transmitted through the directory while the tag field is transmitted through cache tags, allowing complete address information to be conveyed without requiring all address bits to be transmitted through every wire in the system.
3Measurement precision
If full addresses are operated on by logic gates, then address processing accuracy is improved, but logic gate delay increases limiting clock speed
Solution Approach 1:
Address processing operations are segmented and distributed across different structures. The directory operates on the index field while cache tags operate on the tag field, allowing address processing to be completed through simpler, faster operations on smaller data widths rather than full-width address operations, thereby reducing logic gate delay and increasing clock speed.
4Adaptability or versatility
If directory size grows to track more agents, then system coherency tracking capability is improved, but directory access time increases
Solution Approach 1:
The directory structure is segmented into multiple directory segments, each tracking a subset of agents. This segmentation allows the directory to scale to track more agents while maintaining manageable access times for individual segments, as the lookup process can be completed within a smaller segment rather than searching through a monolithic large directory.
Solution Approach 2:
The patent introduces the index field as an additional dimension that enables direct indexing into directory segments. This dimensional addition allows O(1) access time to the appropriate directory segment based on the index, eliminating the need to search through the entire directory structure even as the number of tracked agents grows.
Data Source
AI summary
A system and method are disclosed that include recovery of the system directory when an uncorrectable error is detected. According to the various aspects and embodiments of the invention, the system and method disclosed can manage single bit error detection and two-bit error detection.