Directory-Ordered Release Consistency for Low-Latency Coherence
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Solution Overview
Problem
The communication between processing units in computing systems, particularly due to repeated acknowledgement messages in source ordering, leads to significant latency, increased interconnect traffic, and energy consumption, impacting system performance.
Innovation Solution
Implement directory ordering by using relaxed store messages with epoch numbers and counters to enforce release consistency, reducing the number of messages and acknowledgments needed, and enabling scalable coherence across multiple directories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source ordering is used to ensure release consistency, then memory consistency is maintained, but latency increases due to repeated acknowledgement messages
Solution Approach 1:
The patent extracts the ordering enforcement mechanism from the source processor and relocates it to the cache directory. The source processor no longer needs to send repeated acknowledgements for each relaxed write request, as the directory independently tracks and enforces ordering based on embedded epoch numbers and counters in the message stream.
Solution Approach 2:
The cache directory acts as an intermediary that receives relaxed write requests with epoch information, tracks the ordering state, and autonomously enforces release consistency without requiring continuous feedback to the source processor. This mediator approach eliminates the harmful feedback loop of repeated acknowledgements.
2Reliability
If source ordering with repeated acknowledgements is used, then release consistency is enforced, but interconnect traffic increases
Solution Approach 1:
The patent removes the acknowledgement messaging from the interconnect traffic by extracting the ordering enforcement function to the cache directory. The source processor sends a single relaxed write request with epoch information per cache line, and the directory handles all subsequent ordering enforcement locally without generating additional interconnect traffic.
3Reliability
If source ordering with repeated acknowledgements is used, then release consistency is maintained, but energy consumption increases
Solution Approach 1:
The patent converts the potentially harmful repeated acknowledgement traffic into a beneficial single-message approach with embedded epoch information. The epoch number and counter mechanism embedded in the initial relaxed write request enable the cache directory to enforce ordering without additional energy-consuming acknowledgements, effectively turning the messaging overhead into an efficient embedded metadata approach.
4Reliability
If source ordering is used, then ordering guarantees are provided, but device complexity increases due to tracking mechanisms
Solution Approach 1:
The patent transfers the tracking complexity from the source processor to the cache directory. The directory maintains the epoch number and counter state for each cache line, acting as a centralized mediator that manages ordering guarantees. This relocates the complexity burden to a component already responsible for cache coherence management.
Solution Approach 2:
The cache directory is enhanced with multi-functionality to handle both traditional cache coherence protocols and the new epoch-based ordering enforcement. By integrating release consistency enforcement into the existing directory structure, the patent avoids duplicating tracking mechanisms in multiple components.
Data Source
AI summary
Various embodiments include techniques for inter-processor communication. The techniques include generating a relaxed store message that comprises a first epoch number, incrementing a first counter associated with the first epoch number, and transmitting the relaxed store message to a first directory included in a cache.