Directory Update Policy for Multiprocessor Cache Coherency
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Solution Overview
Problem
Directory-based cache coherency protocols in multiprocessor systems face inefficiencies due to high memory bandwidth and power consumption, particularly in systems using DRAM memory for directory updates, where write bandwidth often exceeds read bandwidth, leading to poor memory utilization.
Innovation Solution
Implementing a specialized directory update policy that prohibits E-to-I directory state transitions in local memory regions, utilizing content-addressable memory to identify local memory regions and reducing unnecessary directory updates by avoiding changes to the directory state when cache lines are primarily owned by a single processor thread.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If directory-based cache coherency protocols are used in multiprocessor systems, then cache coherency is maintained, but memory bandwidth consumption and power consumption increase significantly
Solution Approach 1:
The patent applies local quality by differentiating between local memory regions and non-local memory regions. For local memory regions, E-to-I directory transitions are prohibited, allowing caches to retain exclusive state longer. This localized policy reduction reduces unnecessary directory updates and memory transactions, thereby decreasing memory bandwidth consumption and power usage while maintaining coherency for locally-owned cache lines.
2Reliability
If directory updates are performed for every cache access, then cache coherency is maintained, but write bandwidth exceeds read bandwidth leading to poor memory utilization
Solution Approach 1:
The patent implements local quality by introducing a policy that specifically targets local memory regions. In these regions, E-to-I directory transitions are prohibited, which reduces the frequency of directory updates and memory writes. This selective approach maintains coherency where needed while reducing unnecessary write operations in local regions, thereby improving overall memory utilization efficiency and balancing write bandwidth consumption.
3Use of energy by moving object
If on-chip directory cache is implemented, then external memory bandwidth is reduced, but ASIC costs and on-chip power requirements increase
Solution Approach 1:
The patent applies partial action by implementing a selective directory update policy that prohibits only E-to-I transitions in local memory regions, rather than implementing a complete on-chip directory cache. This partial measure reduces external memory bandwidth consumption and power requirements for directory updates without incurring the full ASIC cost and design complexity of an on-chip directory cache, achieving a cost-effective compromise.
Data Source
AI summary
Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache including an entry for each of a plurality of coherency units, each coherency unit included in a memory block representing a contiguous portion of the plurality of memory resources. A controller is operably connected to the interconnect fabric. The controller is configured to control a portion of the plurality of memory resources, and has a comparator configured to identify whether a memory block is local. If the memory block is local, the controller is configured to set a state of the directory to exclusive for a write transaction. If the memory block is not local, the controller is configured to set the state to invalid for a write transaction.