Dirty Cache State Management Across CPU Resets
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Solution Overview
Problem
Existing data storage systems face challenges in maintaining data integrity and efficiency during write operations, particularly in scenarios where storage processors fail or experience CPU resets, leading to issues with cache management and data consistency across mirrored caches.
Innovation Solution
The method involves caching write data in one storage processor's cache, updating state information to indicate valid, dirty, or prepared states, and then mirroring this data to a second storage processor, ensuring transactional commitment and atomicity across both caches, even in the event of failures or resets, by using direct memory access and interprocessor messaging to maintain cache coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write data is cached in storage processor cache before being written to storage devices, then write operation speed is improved, but data integrity and cache coherence may be compromised during processor failures or resets
Solution Approach 1:
The patent applies preliminary action by setting cache pages to a 'prepared' state before actual write operations occur. This prepared state marks the cache page as containing valid data that needs to be committed, allowing the system to quickly determine whether to overwrite or preserve data without performing full validation during the write operation itself. This pre-marking mechanism enables faster writes while maintaining data integrity through the prepared state tracking.
Solution Approach 2:
The patent implements feedback through inter-processor messaging that communicates cache state information between storage processors. When one processor writes data to a cache page, it sends feedback messages to mirror processors indicating the cache page state (prepared, dirty, or invalid). This feedback mechanism ensures all processors have consistent views of cache coherence, resolving the reliability concern while maintaining high write speeds through efficient state synchronization.
2Stability of the object's composition
If cache pages are immediately merged after write operations, then cache coherence is maintained, but processing overhead and time are increased
Solution Approach 1:
The patent applies preliminary action by pre-marking cache pages with state information (prepared, dirty, invalid) before actual merge operations are needed. This state marking is done during the write operation itself, so when merges are eventually performed, the system can quickly identify which pages need merging based on their pre-marked states rather than performing complex coherence checks at merge time. This reduces processing overhead while maintaining coherence.
Solution Approach 2:
The patent implements dynamics by making cache page state information dynamic and adaptable. The cache pages can transition between different states (invalid, prepared, dirty) based on write operations and merge status. This dynamic state tracking allows the system to defer merge operations until appropriate times while still maintaining coherence, as the state information provides real-time guidance on which pages require merging without requiring immediate action.
3Reliability
If transaction commitment processing is performed synchronously across mirrored caches, then data consistency is ensured, but system response time and throughput are reduced
Solution Approach 1:
The patent applies preliminary action by setting the 'prepared' state on cache pages before transaction commitment is fully completed. This allows the system to acknowledge write operations to hosts more quickly, as the prepared state indicates the data is ready for commitment. The actual commitment processing can then proceed asynchronously or be batched, improving throughput while maintaining consistency through the prepared state tracking that ensures all necessary pages are identified for commitment.
Solution Approach 2:
The patent implements continuity of useful action by allowing write operations to proceed and be acknowledged while transaction commitment processing continues in the background. The inter-processor messaging system maintains continuous synchronization of cache states between mirrored processors, ensuring data consistency is preserved even as the system processes multiple transactions overlapping in time. This continuous state synchronization enables higher throughput without sacrificing consistency.
4Stability of the object's composition
If cache state information is frequently synchronized between storage processors, then cache coherence is maintained, but communication overhead and processing complexity increase
Solution Approach 1:
The patent applies local quality by implementing state information tracking at the individual cache page level rather than requiring global cache state synchronization. Each cache page carries its own state marker (invalid, prepared, dirty), allowing storage processors to independently determine coherence status for specific pages without querying or synchronizing with mirror processors for every operation. This localized state tracking reduces communication overhead while maintaining coherence, and simplifies the system by eliminating complex global synchronization protocols.
Data Source
AI summary
Described are techniques for performing caching. Write operations of a single transactions are received. Write data of the write operations is cached in one or more cache pages of a first cache of a first storage processor. State information is set for the one or more cache pages of the first cache from an invalid state to a prepared state. The write data of the write operations is also stored in a second cache of a second storage processor. A transaction commit state for the single transaction is set indicating that transaction commitment processing for the first cache has commenced and is pending. State information of the one or more cache pages of the first cache is set from the prepared state to a dirty state. The transaction commit state for the single transaction is updated to indicate that the transaction commitment processing for the first cache is completed.