Dirty Cache Line Tracker for Two-Level Memory Bandwidth
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Solution Overview
Problem
Reading an entire cache line to check the state of a dirty bit in a two-level main memory wastes memory bandwidth and consumes system power, as existing methods do not efficiently track dirty cache lines.
Innovation Solution
Implementing a dirty cache line tracker stored in the first level memory of the two-level main memory, which allows for efficient tracking of dirty cache lines and bypasses cache lookup, thereby decoupling battery power and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire cache line is read to check the dirty bit, then the dirty bit state can be determined, but memory bandwidth is wasted and system power is consumed
Solution Approach 1:
The patent extracts the dirty bit information from the full cache line data by implementing a separate dirty cache line tracker that independently monitors and records dirty bit states. This allows the system to check only the tracker entry rather than reading the entire cache line, thereby extracting only the necessary information and avoiding unnecessary power consumption and bandwidth usage.
Solution Approach 2:
The patent introduces a dirty cache line tracker as an intermediary data structure that mediates between cache line modifications and dirty bit checking. The tracker stores pre-computed dirty bit states, serving as an intermediate layer that eliminates the need to read full cache lines for status verification, thus reducing power consumption while maintaining detection accuracy.
2Measurement precision
If the entire cache line is read to check the dirty bit, then the dirty bit state can be determined, but memory bandwidth is wasted
Solution Approach 1:
The patent extracts only the essential dirty bit status information from the cache line by maintaining a separate tracker that records modification states. This extraction approach allows the system to obtain accurate dirty bit detection without the overhead of reading entire cache lines, thereby preventing memory bandwidth waste.
Solution Approach 2:
The patent applies partial action by implementing a minimal tracking mechanism that monitors only the necessary aspect (dirty bit state) rather than processing the complete cache line data. The tracker uses minimal storage space and requires minimal read operations, achieving sufficient functionality with less than full cache line access.
3Use of energy by moving object
If a dirty cache line tracker is implemented, then memory bandwidth usage and power consumption are reduced, but additional tracking infrastructure is required
Solution Approach 1:
The patent merges the dirty cache line tracker with existing cache management structures, integrating the tracking functionality into the cache controller or memory management unit. By combining the tracker with existing infrastructure rather than creating a completely separate system, the patent reduces overall device complexity while still achieving power and bandwidth savings.
Solution Approach 2:
The dirty cache line tracker is designed to serve multiple functions: it tracks dirty bits for write-back operations, provides information for cache coherence protocols, and supports memory management decisions. This multi-functionality allows the same tracking infrastructure to benefit multiple system components, reducing the relative complexity overhead.
Data Source
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Figure 3A~3B
AI summary
A two-level main memory that includes a persistent memory (132) and a cache (136) is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker (150). The dirty cache line tracker is stored in the cache and can be cached in a memory controller (138) for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.