Dirty Line Limiter Protocol for Cache Flush Time Reduction
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Solution Overview
Problem
Large L3 caches cause significant performance degradation due to time-consuming brute-force cache flushing at the beginning and end of parallel loops and during hardware checkpoints, with existing write-back and write-through cache policies leading to traffic bottlenecks and inefficiencies.
Innovation Solution
Implementing a dirty line limiter protocol that populates and de-populates directory entries based on a pre-defined limit to manage cache write-backs, reducing cache flush time without increasing write-back traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If brute-force cache flushing is used at the beginning and end of parallel loops, then all remote data is flushed from caches ensuring visibility to all processors, but cache flush time increases substantially causing performance degradation
Solution Approach 1:
The patent extracts only the necessary dirty cache lines for flushing based on actual modification status, rather than flushing the entire cache. The directory tracks which specific cache lines are dirty, allowing selective flushing of only those lines that need to be written back to memory, thereby reducing flush time while maintaining data visibility.
Solution Approach 2:
The patent performs preliminary tracking of dirty cache lines throughout the loop execution using a directory structure. By maintaining this information during loop execution, the system prepares the necessary flush information in advance, allowing efficient targeted flushing at the end of the loop rather than brute-force flushing of the entire cache.
2Reliability
If write-through cache policy is used, then cache flushing is never needed ensuring data consistency, but write-through traffic exceeds the traffic capacity of interconnect
Solution Approach 1:
The patent applies different cache policies to different cache lines based on their access patterns and dirtiness status. Instead of a uniform write-through policy for all cache lines, the system allows write-back for dirty lines while maintaining write-through characteristics for clean lines, optimizing interconnect traffic while preserving data consistency where needed.
Solution Approach 2:
The patent implements a directory that provides feedback about the actual state of cache lines (dirty or clean). This feedback mechanism allows the system to make informed decisions about which cache lines require flushing, avoiding unnecessary write-through traffic for clean lines while ensuring proper flushing of dirty lines, thus optimizing interconnect utilization.
3Productivity
If write-back cache policy is used, then write-through traffic is eliminated, but streaming data causes bursty write-backs creating bottlenecks on the interconnect
Solution Approach 1:
The patent implements periodic flushing of dirty cache lines at structured intervals (beginning and end of parallel loops, and at hardware checkpoints) rather than allowing uncontrolled bursty write-backs. This periodic action smooths interconnect traffic by concentrating flushes at predictable moments when they are most efficient, rather than creating random bursts that bottleneck the interconnect.
4Ease of operation
If eager write-back is used, then bursty write-backs causing traffic bottlenecks are reduced, but large amounts of cache lines still need to be flushed at the beginning and end of parallel loops or upon executing hardware checkpoint functions
Solution Approach 1:
The patent extracts and identifies only the specific dirty cache lines that need flushing at loop boundaries and checkpoints, rather than flushing all cache lines. The directory maintains precise tracking of dirty lines, allowing the system to flush only the necessary subset of dirty lines at these critical points, significantly reducing flush time compared to flushing the entire cache.
Data Source
AI summary
The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.