DIRW Matrix Verification for Implementation-Dependent Registers
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Solution Overview
Problem
Conventional logic verification methods for hardware design are inefficient due to inadequate parameter settings, which can lead to oversight in verifying implementation-dependent registers not specified in the design specifications, resulting in incomplete verification coverage.
Innovation Solution
A computer-readable recording medium stores a verification supporting program that creates a DIRW matrix to record state transitions and validity information for registers, acquires implementation information and register lists, and generates a control data flow graph to extract and verify paths for both internal and implementation-dependent registers, determining valid state transitions and calculating parameter values for comprehensive verification scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic verification methods are used with parameter settings based on design specifications, then verification can be executed according to the specified function, but verification coverage is insufficient because implementation-dependent registers not specified in the design are not covered
Solution Approach 1:
The verification scenario creation apparatus performs preliminary analysis of the hardware design to automatically identify implementation-dependent registers before verification execution. By pre-generating verification scenarios that include these registers, the system ensures comprehensive coverage without requiring manual intervention during the verification process itself.
Solution Approach 2:
The verification scenario creation apparatus acts as an intermediary between the hardware design and the verification execution. It analyzes the hardware design to extract implementation-dependent registers and automatically generates appropriate verification scenarios, thereby bridging the gap between specification-based design and implementation-specific verification needs.
2Ease of operation
If random parameter substitution is used in verification scenarios, then verification execution is simple, but verification completeness is poor as not all verification examples are covered
Solution Approach 1:
The system automatically determines appropriate parameter values for verification scenarios based on the analyzed hardware design and identified implementation-dependent registers. Instead of random substitution, parameters are systematically set to cover relevant verification cases, ensuring both completeness and automated generation.
3Measurement precision
If manual creation of verification scenarios is performed to cover specific registers, then verification precision can be improved, but verification efficiency decreases due to time-consuming manual processes
Solution Approach 1:
The verification scenario creation apparatus performs self-service by automatically analyzing the hardware design, identifying implementation-dependent registers, and generating appropriate verification scenarios without requiring manual intervention. This automation maintains high verification precision while significantly improving efficiency.
Solution Approach 2:
The system replaces the manual mechanical process of verification scenario creation with an automated computational process. The verification scenario creation apparatus uses algorithmic analysis to identify registers and generate scenarios, substituting human effort with automated processing while maintaining or improving verification quality.
Data Source
AI summary
In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.