Disaggregated Base Die Stacking for Higher-Yield Semiconductor Arrays
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Solution Overview
Problem
Conventional stacked semiconductor die architectures face issues with decreasing yield and increased fabrication time due to mounting multiple dies on a single monolithic base die, which requires time-intensive joining operations.
Innovation Solution
The architecture involves disaggregating the monolithic base die into multiple base dies and using a carrier wafer with embedded semiconductor dies, reducing the number of joining operations and incorporating passive semiconductor devices to improve yield and reduce fabrication time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple stacked semiconductor dies are mounted on a single monolithic base die, then the array size of stacked dies is increased, but the yield of the base die diminishes and fabrication time increases
Solution Approach 1:
The patent divides the monolithic base die into multiple smaller base dies, each capable of supporting a subset of the stacked semiconductor dies. This segmentation prevents yield loss affecting the entire array if a defect is found in one base die, while still achieving the desired large array size through parallel processing of multiple smaller units.
2Quantity of substance
If multiple stacked semiconductor dies are mounted on a single monolithic base die, then the array size of stacked dies is increased, but the fabrication time increases due to time-intensive joining operations
Solution Approach 1:
By segmenting the base die into multiple smaller units, the patent enables parallel processing during fabrication. Multiple base dies can be prepared, tested, and assembled simultaneously rather than sequentially on a single large monolithic base die, significantly reducing overall fabrication time.
Solution Approach 2:
The patent implements preliminary testing and validation of individual base dies before final assembly with stacked semiconductor dies. This preliminary action allows for early detection of defects, preventing rework of entire large arrays and reducing fabrication time by avoiding late-stage failures.
3Quantity of substance
If multiple stacked semiconductor dies are mounted on a single monolithic base die, then the array size of stacked dies is increased, but the fabrication cost increases
Solution Approach 1:
The patent segments the base die into multiple smaller units that can be manufactured using standard fabrication processes, avoiding the need for expensive large-wafer processing equipment. This segmentation enables cost-effective production while achieving large array sizes through assembly of multiple smaller units.
Solution Approach 2:
The patent implements a strategy where individual base dies are tested and validated independently before final assembly. If a defect is detected in a base die, only that specific unit is discarded rather than the entire large array, maximizing yield recovery and reducing fabrication costs.
Data Source
AI summary
Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.