Disaggregated Computing Address Mapping via Interconnect Interface
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Solution Overview
Problem
In disaggregated computer architectures, there is a difficulty in allowing virtual machines to access accelerators implemented on other system nodes, which hinders efficient use of hardware resources and leads to performance issues due to the complexity of implementing device pass-through.
Innovation Solution
A disaggregated computing architecture is implemented, where a compute node with an interconnect interface and an accelerator node are linked by an interconnection network, enabling a guest device driver to access the accelerator's physical device through a uniform physical address range, with a memory management unit mapping guest physical addresses to the accelerator's memory, and a global system orchestrator configuring the address mappings for device pass-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device pass-through is implemented in disaggregated architecture, then virtual machines can access accelerators on other system nodes with near-native performance, but the complexity of implementing address space mapping between independent system nodes increases
Solution Approach 1:
The interconnection network serves as an intermediary between system nodes with independent physical address spaces. It provides a uniform physical address range that acts as a common language for address translation, enabling the compute node to map host physical addresses to accelerator device registers across network boundaries without requiring complex direct address translation between independent address spaces.
Solution Approach 2:
The address translation function is segmented and distributed across multiple components: the interconnect interface on the compute node handles host physical address to uniform physical address mapping, while the memory management unit on the accelerator node handles guest virtual address to physical address mapping. This segmentation allows each component to focus on a specific translation task, reducing overall complexity.
2Adaptability or versatility
If traditional emulation methods are used to allow virtual machines to access hardware devices, then hardware accessibility is improved, but processing speed deteriorates due to software emulation overhead
Solution Approach 1:
The physical accelerator device is extracted from the accelerator node and made directly accessible to the virtual machine through device pass-through. By removing the emulation layer and establishing a direct access path through the interconnection network with proper address mapping, the system achieves both hardware accessibility and native processing speed.
3Productivity
If disaggregated architecture with independent physical address spaces is used, then hardware resource utilization is improved, but device pass-through implementation becomes difficult
Solution Approach 1:
The interconnection network is designed with universal address translation capabilities that work across different system nodes with independent address spaces. The uniform physical address range provides a universal interface that enables device pass-through functionality to be implemented consistently across the disaggregated architecture, making the implementation easier and more scalable.
Data Source
AI summary
The present disclosure relates to a disaggregated computing architecture comprising: a first compute node (302) comprising an interconnect interface (310); an accelerator node (304) comprising a physical device (402); and an interconnection network (308) linking the first compute node (302) and the accelerator node (304), wherein: the first compute node (302) executes a host operating system (410) and instantiates a first virtual machine (VM) executing a guest device driver (406) for driving the physical device; one or more input registers of the physical device are accessible via a first uniform physical address range (upa_a_devctl) of the interconnection network (308); and the interconnect interface (310) of the first compute node (302) is configured to map a host physical address range (hpa_c_devctl) of the host operating system (410) to the first uniform physical address range (upa_a_devctl).