Disaggregated Memory Over Optical Channels for Low-Latency Computing
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Solution Overview
Problem
Existing computing systems face inefficiencies in memory utilization due to integration requirements, leading to increased latency and reduced bandwidth when processors need to access memory units, especially for lower complexity operations.
Innovation Solution
A photonic computing system with disaggregated memory units connected through optical channels, where a memory controller performs lower complexity operations in parallel or subsequent to processor operations, reducing latency and increasing memory capacity without integrating processors with memory on a chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory units are integrated with processors on a chip, then access speed is improved, but memory capacity and bandwidth are reduced
Solution Approach 1:
The system divides memory into disaggregated memory units that are physically separated from processors and connected through optical channels. Each memory unit can be independently accessed by multiple processors, enabling both high capacity and fast access through parallel optical connections.
Solution Approach 2:
Optical channels serve as intermediaries between processors and disaggregated memory units, enabling high-speed data transmission without direct physical integration. The optical network fabric acts as a mediator that connects multiple processors to multiple memory units, achieving both speed and capacity.
2Loss of time
If processors are physically integrated with memory on a chip, then access latency is reduced, but system complexity increases
Solution Approach 1:
The patent replaces traditional electrical interconnects with optical channels for connecting processors to memory units. This substitution enables higher bandwidth and lower latency while reducing physical constraints and heat generation, thereby lowering overall system complexity despite the disaggregated architecture.
Solution Approach 2:
The system transitions from a two-dimensional chip integration model to a three-dimensional architecture where processors and memory units are distributed in space and connected through optical channels. This dimensional change allows memory units to be placed closer to processors physically while maintaining logical separation, reducing latency without increasing on-chip complexity.
3Productivity
If memory bandwidth is increased through integration, then data transfer rate is improved, but memory capacity is reduced
Solution Approach 1:
The optical network fabric provides a universal communication infrastructure that can simultaneously serve multiple processors and multiple memory units. Each optical channel can dynamically allocate bandwidth to different processor-memory pairs, enabling high data transfer rates while supporting large total memory capacity across the system.
Data Source
AI summary
Described herein are embodiments of a photonic computing system comprising one or more processors in communication with disaggregated memory through one or more optical channels. The disaggregated memory comprises multiple memory units placed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processor(s). The disaggregated memory includes a memory controller for reading and writing data to/from the memory units. The memory controller may be configured to perform processing in concert with the processor(s).