Disaggregated Memory Pipe Using Shared Rings and Ownership Polling
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Solution Overview
Problem
In computing systems with disaggregated memory, maintaining cache coherence becomes challenging as the number of connected hosts increases, leading to inefficient communication and network performance issues due to the need for costly cache flushes and out-of-band messaging.
Innovation Solution
A communication protocol using circular buffers and descriptor ownership to manage data ownership between processors, allowing efficient communication without cache coherence, reducing the reliance on out-of-band messaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence protocols are used to ensure data consistency across multiple CPUs accessing disaggregated memory, then data consistency is maintained, but system scalability deteriorates and network performance deteriorates due to the inability to scale distributed cache coherent traffic
Solution Approach 1:
The patent extracts the cache coherence requirement from the system by implementing a polling-based ownership model where processors explicitly query ownership status rather than relying on implicit cache coherence protocols. This removes the scalability bottleneck while maintaining data consistency through explicit ownership tracking.
Solution Approach 2:
The patent implements feedback mechanisms through polling processes where processors continuously query the ownership status of memory regions. This feedback loop ensures that processors only access memory when they have ownership, maintaining consistency without requiring full cache coherence protocols that would limit scalability.
2Reliability
If cache flush operations are performed frequently to maintain data consistency in non-cache-coherent environments, then data consistency is maintained, but communication efficiency deteriorates due to the costly nature of cache flush operations
Solution Approach 1:
The patent performs preliminary actions by establishing ownership relationships before memory access operations. Processors query ownership status and establish ownership prior to writing or reading memory, preventing the need for subsequent cache flush operations and improving communication efficiency while maintaining consistency.
Solution Approach 2:
The system implements self-service through automatic ownership tracking and polling mechanisms. Processors automatically manage their own ownership status and memory access permissions without requiring external coordination or costly cache flush operations, improving communication efficiency while ensuring consistency.
3Reliability
If out-of-band messaging is used to coordinate turn-based memory access among processors, then data consistency is maintained, but network performance deteriorates due to increased latency and reduced bandwidth from the large number of messages required
Solution Approach 1:
The patent merges the ownership tracking and memory access coordination functions into a unified polling mechanism that operates within the existing memory fabric. This eliminates the need for separate out-of-band messaging infrastructure, reducing network overhead and improving speed while maintaining data consistency through integrated ownership management.
Solution Approach 2:
The polling mechanism serves multiple functions simultaneously: it tracks ownership status, coordinates memory access, and ensures data consistency. This multi-functional approach replaces the need for dedicated out-of-band messaging systems, improving network performance by reducing the number of messages required while maintaining reliability.
Data Source
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AI summary
Processor-to-processor communication is provided by using a non-cache-coherent disaggregated memory. The communication between a first processor and a second processor uses a pipe with three circular buffers (rings): a first ring at a first memory of a first computer that includes the first processor, a second ring at a second memory of a second computer that includes the second processor, and a third (shared) ring at the disaggregated memory that is shared by the first and second processors. The first processor uses the pipe to write a descriptor (containing the data and an ownership value) to the shared ring, and the second processor performs a polling process to determine if the ownership value corresponds to the second processor so that the second processor can act on (e.g., copy and modify) the data in the descriptor.