Disaggregated Memory Pool Address Mapping
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Solution Overview
Problem
Data centers face inefficiencies due to resource stranding, where compute nodes are underutilized or idle despite having available resources, leading to suboptimal resource allocation and increased complexity in memory addressing.
Innovation Solution
Implementing a disaggregated memory pool where volatile memory is decoupled from individual compute nodes and made available as a flexible resource pool, allowing nodes to request memory as needed and using memory address mapping techniques to efficiently allocate and manage memory across multiple nodes and memory control systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is tightly coupled to individual compute nodes, then memory access latency is minimized, but resource utilization efficiency deteriorates due to resource stranding
Solution Approach 1:
The patent segments the memory system into compute node-attached volatile memory and a shared disaggregated memory pool. This segmentation allows compute nodes to have fast local memory access while also having access to a pooled memory resource that can be dynamically allocated to any node, thereby preventing resource stranding and improving overall utilization efficiency.
Solution Approach 2:
The patent introduces a memory control system as an intermediary between compute nodes and the disaggregated memory pool. This intermediary manages memory allocation, addressing, and access coordination, enabling efficient resource sharing while maintaining performance through mechanisms like address translation and allocation slicing.
2Productivity
If memory is disaggregated into a pooled resource, then resource utilization efficiency improves, but memory addressing complexity increases
Solution Approach 1:
The memory control system serves as an intermediary that handles the complexity of address translation and memory allocation. It receives allocation slice requests from compute nodes, determines appropriate memory locations in the pooled resources, and manages the mapping between host physical addresses and pooled memory addresses, thereby simplifying the addressing complexity for the compute nodes.
Solution Approach 2:
The patent divides the memory address space into allocation slices, where each slice corresponds to a specific portion of the disaggregated memory pool allocated to a particular compute node. This segmentation allows for simplified address management by creating discrete, manageable memory regions rather than dealing with a monolithic address space.
3Ease of manufacture
If compute nodes are allocated fixed memory resources, then allocation simplicity is maintained, but adaptability to workload changes deteriorates
Solution Approach 1:
The patent implements dynamic memory allocation where compute nodes can request and be allocated memory resources from the pooled volatile memory based on their current workload requirements. This dynamic allocation mechanism allows the system to adapt to changing workloads by allocating memory to nodes that need it most, while maintaining a simplified allocation interface through the memory control system.
Solution Approach 2:
The disaggregated memory pool serves multiple compute nodes universally, allowing any node to access pooled memory resources as needed. This multi-functional approach replaces fixed dedicated memory allocations with a shared resource that can serve any compute node's workload requirements, thereby improving adaptability while maintaining allocation simplicity through centralized management.
Data Source
AI summary
A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.