Disaggregated Memory Communication Using Ownership-Based Shared Rings
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Solution Overview
Problem
In computing systems with disaggregated memory, maintaining cache coherence becomes challenging when a large number of hosts are connected, leading to inefficiencies and network performance issues due to the need for costly cache flushes and out-of-band messaging.
Innovation Solution
A communication protocol using circular buffers and descriptor ownership to manage data ownership between processors, allowing them to write to shared disaggregated memory without requiring cache coherence, thereby reducing the need for out-of-band messaging and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence protocols are used to ensure data consistency across multiple CPUs accessing disaggregated memory, then data consistency is maintained, but system complexity and communication overhead increase significantly
Solution Approach 1:
The patent extracts the cache coherence requirement by implementing a polling-based ownership model where processors explicitly query ownership status before accessing memory. This removes the need for complex distributed cache coherence protocols while maintaining data consistency through explicit ownership tracking and polling mechanisms.
Solution Approach 2:
The patent introduces an intermediary ownership indicator mechanism that mediates access between multiple processors and disaggregated memory. Instead of direct cache coherence protocols, processors poll ownership indicators to determine who should access the memory, acting as an intermediary control layer that simplifies the interaction model.
2Reliability
If out-of-band messaging is used to coordinate turn-based writing to disaggregated memory, then data corruption is prevented, but network performance deteriorates due to increased latency and bandwidth consumption
Solution Approach 1:
The patent merges the ownership coordination function into the existing memory access fabric by implementing polling mechanisms that utilize the same communication infrastructure. Instead of separate out-of-band messaging channels, ownership status is queried through the existing memory fabric, combining coordination and data transfer functions to reduce latency and network overhead.
3Reliability
If frequent cache flushes are performed to maintain consistency in non-cache-coherent systems, then data consistency is maintained, but system performance decreases due to costly flush operations
Solution Approach 1:
The patent performs preliminary actions by having processors poll ownership status before memory access operations. This proactive checking prevents inconsistent access patterns that would require costly cache flushes, as processors only access memory when they have confirmed ownership, eliminating the need for frequent consistency maintenance operations.
Data Source
AI summary
Processor-to-processor communication is provided by using a non-cache-coherent disaggregated memory. The communication between a first processor and a second processor uses a pipe with three circular buffers (rings): a first ring at a first memory of a first computer that includes the first processor, a second ring at a second memory of a second computer that includes the second processor, and a third (shared) ring at the disaggregated memory that is shared by the first and second processors. The first processor uses the pipe to write a descriptor (containing the data and an ownership value) to the shared ring, and the second processor performs a polling process to determine if the ownership value corresponds to the second processor so that the second processor can act on (e.g., copy and modify) the data in the descriptor.