Discharge Circuit for Semiconductor Memory Read Margin
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Solution Overview
Problem
Semiconductor memory devices, particularly SRAM, face a challenge in maintaining read operation characteristics of half-selected memory cells while boosting the write operation characteristics of selected memory cells, leading to reduced read margins due to voltage differences between bit lines.
Innovation Solution
Incorporating a discharge circuit with a connector, dummy memory cell, and bit line clamp circuit to manage voltage differences between bit lines during read and write operations, ensuring stable data retention in half-selected memory cells by controlling voltages based on data levels stored in latch nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the word line voltage is boosted to improve write operation characteristics of a selected memory cell, then the write operation characteristics are improved, but the read operation characteristics of a half-selected memory cell deteriorate
Solution Approach 1:
A discharge circuit is introduced as an intermediary component between the bit line and ground. This discharge circuit includes a discharge transistor that is activated during write operations to provide an additional discharge path for the bit line, thereby managing the voltage levels and protecting the half-selected memory cells from voltage spikes caused by word line boosting.
Solution Approach 2:
The invention dynamically changes the voltage parameters of the bit line by controlling the discharge circuit. During write operations, the discharge circuit is activated to lower the bit line voltage more effectively, preventing excessive voltage buildup that would harm half-selected cells. The discharge circuit transitions between active and inactive states based on operation type, optimizing voltage control for different operational modes.
2Speed
If voltage control is applied to improve write operation, then write speed is improved, but voltage difference between bit lines increases causing read margin degradation
Solution Approach 1:
The discharge circuit serves as a mediator that balances the voltage between the bit line and ground. By introducing this intermediate discharge path, the circuit prevents excessive voltage differences from developing between bit lines during write operations, thereby maintaining read margins while preserving write speed improvements.
Solution Approach 2:
The discharge circuit provides dynamic voltage control by adjusting the discharge path activation based on operational requirements. During write operations, the discharge transistor is activated to quickly equalize bit line voltages, preventing large voltage differences that would degrade read margins, while allowing fast write operations to proceed.
Data Source
AI summary
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.