Discharging Circuitries for Bit Line Pairs in Memory Arrays
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Solution Overview
Problem
Integrated circuits face significant power consumption issues due to the discharging of unselected bit line pairs during memory operations, particularly in memory arrays with high aspect ratios, where the number of unselected bit line pairs being discharged is substantial, leading to increased dynamic power requirements.
Innovation Solution
The implementation of discharging circuitries that selectively discharge bit line pairs, using a combination of transistors and diode devices to limit the discharge of unselected bit line pairs to a threshold voltage, thereby reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pre-charge circuitry is enabled to pre-charge all bit line pairs during idle periods, then the bit lines are ready for rapid read/write operations, but significant power is consumed due to discharging of unselected bit line pairs during memory operations
Solution Approach 1:
The patent segments the bit line pairs into selected and unselected groups during memory operations. Discharging circuitry is selectively activated only for unselected bit line pairs, while selected bit line pairs maintain their charge. This segmentation allows the system to preserve the pre-charged state of bit lines needed for upcoming operations while discharging only those that are not currently selected, thereby reducing unnecessary power consumption without compromising operational speed.
Solution Approach 2:
The patent changes the voltage parameter of unselected bit line pairs from a high pre-charged voltage to a discharged voltage (or vice versa) during memory operations. By dynamically controlling the voltage state of unselected bit line pairs through selective discharging circuitry, the system minimizes power consumption while maintaining the readiness of selected bit line pairs for rapid operations.
2Quantity of substance
If the number of unselected bit line pairs is increased in memory arrays with high aspect ratios, then the memory array capacity increases, but the power consumption due to discharging of unselected bit line pairs increases substantially
Solution Approach 1:
The patent applies segmentation by dividing the large number of bit line pairs into selected and unselected categories. For memory arrays with high aspect ratios that have many unselected bit line pairs, the discharging circuitry is selectively enabled only for unselected pairs, allowing the system to scale memory capacity without proportionally increasing power consumption from discharging operations.
Solution Approach 2:
The patent extracts the discharging function from all bit line pairs and applies it only to unselected bit line pairs. By separating the discharging operation from the selected bit line pairs, the system can accommodate larger memory arrays with more unselected bit line pairs while minimizing the power impact by limiting discharging to only those pairs that do not need to maintain their charge.
3Use of energy by moving object
If discharging circuitry is selectively applied to unselected bit line pairs, then power consumption is reduced, but the circuit complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the discharging circuitry to serve dual purposes: it can be selectively enabled for unselected bit line pairs during certain operations and disabled during others. This universal circuit design allows the same discharging circuitry to adapt to different operational modes, reducing the need for entirely separate circuits and thereby limiting the increase in overall circuit complexity.
Solution Approach 2:
The patent introduces dynamic control of the discharging circuitry through selective enabling and disabling based on operation type. The discharging circuitry transitions between active and inactive states, allowing the system to optimize power consumption during operations with unselected bit line pairs while maintaining simplicity during operations where all bit lines are selected. This dynamic behavior reduces the effective complexity by using control signals rather than requiring permanently active circuits.
Data Source
AI summary
Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.