Disciplined Clock Frequency Correction via GNSS Feedback
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Solution Overview
Problem
Conventional radio controlled clocks periodically synchronize with external reference sources but do not control the frequency of their oscillators, leading to significant time errors between synchronizations, and lack redundancy for critical applications like stock market transactions that require high accuracy and fail-safe timekeeping.
Innovation Solution
A disciplined clock system that uses a time receiver to receive a common view signal from GNSS satellites, a local clock to produce a timing signal, and a controller to determine and apply frequency corrections based on time differences with a reference clock, ensuring continuous synchronization and redundancy across multiple reference clocks and satellite systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional radio controlled clocks periodically synchronize with external reference sources, then time synchronization is achieved, but significant time errors accumulate between synchronizations and frequency control is lost
Solution Approach 1:
The patent implements a feedback control system where the controller continuously monitors the time difference between the local clock and reference clock, calculates frequency correction values, and applies them to the local oscillator. This closed-loop feedback mechanism eliminates time errors between synchronizations by maintaining continuous frequency control, resolving the contradiction between periodic synchronization accuracy and reliability between synchronizations.
Solution Approach 2:
The patent transitions from periodic discontinuous synchronization to continuous frequency control. The controller continuously calculates time differences, generates frequency correction values, and applies them to the local oscillator without interruption. This continuous action ensures constant timekeeping accuracy and eliminates the accumulation of errors between periodic synchronizations.
2Device complexity
If a single reference clock is used for timekeeping, then device complexity is reduced, but redundancy and fail-safe capability are lost
Solution Approach 1:
The patent changes the operational parameter of the reference clock system from single-source to multi-source configuration. The controller is configured to receive and process signals from multiple reference clocks and GNSS satellites, dynamically selecting and switching between references based on availability and quality metrics. This parameter change provides fail-safe redundancy while managing complexity through systematic signal processing.
Solution Approach 2:
The patent implements prior cushioning by pre-configuring multiple reference clocks and establishing backup pathways before failures occur. The controller continuously monitors the health and availability of each reference source and automatically switches to backup references when primary sources fail, providing fail-safe capability without requiring complex manual intervention during critical failures.
3Measurement precision
If frequency correction is applied continuously to maintain synchronization, then time accuracy is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent implements multi-functionality in the controller that performs multiple tasks: receiving signals from multiple reference clocks and GNSS satellites, calculating time differences, generating frequency correction values, applying corrections to the local oscillator, and monitoring system health. This universal controller consolidates what could be separate complex subsystems into a single integrated unit, improving timekeeping accuracy while managing overall device complexity.
Data Source
AI summary
A disciplined clock provides a disciplined time and a disciplined frequency synchronous with a reference clock. The disciplined clock includes: a time receiver to: receive a common view signal from the common view clock; and produce a receiver timing signal; a local clock to: receive a frequency correction; and produce a local timing signal; a time interval counter to: receive the receiver timing signal from the time receiver; receive the local timing signal from the lock clock; and determine a time difference between the receiver timing signal and the local timing signal; and a controller to: receive the time difference from the time interval counter; and communicate the frequency correction, based on the time difference, to the local clock.