Discontinuous Isolation Well Structure for Low-Capacitance ESD Protection

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Solution Overview

Problem

Integrated circuits face damage from electrostatic discharge (ESD) events due to the lack of effective isolation structures in existing semiconductor devices, which can lead to current conduction issues and device failure.

Innovation Solution

A semiconductor substrate with a segmented deep well of opposite conductivity type, formed by ion implantation, is used to create a bidirectional silicon-controlled rectifier structure that includes shallow trench isolation regions and additional wells, providing enhanced electrical isolation and reduced capacitance, thereby protecting against ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a continuous triple-well isolation structure is used, then electrical isolation from substrate is achieved, but capacitance increases and harmonics distortion worsens

Engineering Contradiction:
Improveelectrical isolationVSAvoidcapacitance and harmonics distortion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The continuous isolation well is divided into multiple discrete segmented wells separated by spacing. This segmentation maintains electrical isolation functionality while reducing the total doped volume, thereby decreasing parasitic capacitance and harmonics distortion without sacrificing the essential isolation performance from the substrate

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If a segmented deep well structure is used, then capacitance is reduced, but manufacturing complexity increases

Engineering Contradiction:
ImprovecapacitanceVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The isolation well is segmented into discrete regions with spacing between them, reducing the total doped volume and associated parasitic capacitance. The segmentation is achieved through standard photolithography and ion implantation processes, maintaining manufacturing feasibility while achieving the capacitance reduction goal

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The doping concentration and well depth parameters are optimized for the segmented structure to achieve the desired capacitance reduction while maintaining electrical isolation performance. Process parameters such as implantation energy and dose are adjusted to create the segmented profile using existing fabrication capabilities

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The segmented deep well structure effectively isolates the semiconductor substrate from ESD currents, reducing capacitance and harmonics distortion, and maintaining performance similar to conventional continuous deep well structures while offering improved protection against electrostatic discharge.

Implementation Method 1

The segmented deep well structure effectively isolates the semiconductor substrate from ESD currents, reducing capacitance and harmonics distortion

Methodology Applied
Scientific EffectElectrical isolation: Electrical Resistance

Implementation Method 2

A semiconductor substrate with a segmented deep well of opposite conductivity type, formed by ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20230395714A1Protection device structures with a discontinuous isolation well
Publication Date: 2023.12.07 GLOBALFOUNDRIES US INC
  • US20230395714A1 patent drawing
  • US20230395714A1 patent drawing
  • US20230395714A1 patent drawing

AI summary

Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.