Discontinuous Layer-ID Detector for 3D-IC Stacked Devices
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Solution Overview
Problem
Existing methods for identifying layers in 3D-IC stacked devices are costly and inefficient, especially as the number of stacked chips increases, as they require complex structures and control systems to assign unique identification numbers to each chip.
Innovation Solution
A discontinuous type layer-ID detection method using a circuit scheme with comparators, add/sub circuits, and a plus-one circuit to generate layer IDs by comparing initial layer numbers and assigned numbers, separating chips into even and odd groups based on incremental and decremental quotients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex structures and control systems are used to assign unique identification numbers to each chip, then layer identification accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The detection circuit automatically generates layer IDs by detecting the number of high-impedance states on signal lines, eliminating the need for external complex control systems. The circuit self-identifies layer positions through inherent electrical characteristics of the stacked chips.
Solution Approach 2:
The patent replaces complex mechanical control systems with an electrical detection circuit that uses impedance detection and binary counting mechanisms to identify layers, simplifying the overall system architecture while maintaining identification accuracy.
2Quantity of substance
If the number of stacked chips increases, then storage capacity is improved, but the number of electrodes and identification complexity increase
Solution Approach 1:
The detection circuit uses a universal counting mechanism that can identify any number of layers by detecting high-impedance states, allowing the same circuit architecture to scale with increasing chip stacks without requiring additional electrodes or complexifying the identification system.
Solution Approach 2:
The patent transitions from electrode-based identification to impedance-state-based identification, effectively moving from a physical dimension (number of electrodes) to an electrical state dimension (high-impedance detection), allowing scalable layer identification without increasing electrode count.
3Ease of operation
If traditional layer identification methods are used, then chip selection is achieved, but cost and complexity increase
Solution Approach 1:
The patent employs a cost-effective detection circuit using standard logic components (comparators, adders, counters) that can be easily manufactured and integrated, replacing expensive traditional identification methods while maintaining chip selection capability.
Solution Approach 2:
The detection circuit changes the identification parameter from physical electrode assignment to electrical impedance state detection, enabling cost-effective layer identification by utilizing inherent electrical characteristics of the chips rather than requiring additional identification hardware.
Data Source
AI summary
A 3D-IC detector for each layer of a stacked device with N layer, includes a dividing-two circuit coupled to a (Nā1) signal; a first comparator is coupled to the dividing-two circuit, wherein an input A is coupled to an initial layer number signal, an input B of the first comparator is coupled to an output of the dividing-two circuit; a second comparator is coupled to the initial layer number by an input A of the second comparator, and a num is coupled to an input B of the second comparator; a first Add/sub circuit is coupled to the num via an input A of the first Add/sub circuit, and coupled to the first comparator via an input B of the first Add/sub circuit, to the second comparator via an input +/ā signal of the first Add/sub circuit; and a second Add/sub circuit coupled to the first comparator via an input A of the second Add/sub circuit, to the num via an input B of the second Add/sub circuit.