Discontinuous PMOS FinFET SRAM for Strain and Ion Current Control
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Solution Overview
Problem
Existing FinFET SRAM devices face challenges with SRAM cell write margins and logic circuit speeds, particularly due to high Ion current from continuous fin lines, which affects strain effects and line-end shrinkage control.
Innovation Solution
The implementation of discontinuous P-type FinFET fin lines in SRAM cells arrays and continuous fin lines in logic circuit cells arrays, along with multiple work-function metals and isolation transistors, to manage Ion current and threshold voltage, enhancing SRAM write margins and logic circuit speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If continuous fin lines are used in FinFET SRAM devices, then Ion current is increased, but strain effects are reduced and line-end shrinkage control is affected
Solution Approach 1:
The patent divides the continuous fin line into multiple discontinuous fin lines. Specifically, the PMOS fin lines are segmented into separate sections rather than forming a continuous structure. This segmentation reduces the overall strain effect while maintaining sufficient Ion current for SRAM operation, resolving the contradiction between high Ion current and strain effect control.
2Power
If continuous fin lines are used in FinFET SRAM devices, then Ion current is increased, but line-end shrinkage control is affected
Solution Approach 1:
By segmenting the fin lines into discontinuous sections, the patent reduces the cumulative line-end shrinkage effect that occurs in continuous long fin lines. Each discontinuous segment has its own endpoints, and the total effective length contributing to shrinkage is reduced, improving manufacturing precision while maintaining adequate Ion current.
3Reliability
If FinFET devices are used to improve gate length scaling and intrinsic Vt fluctuation, then device stability is improved, but SRAM cell write margins and chip speeds are reduced
Solution Approach 1:
The patent applies different fin line configurations to different transistor types within the SRAM cell. PMOS transistors use discontinuous fin lines to reduce strain and improve write margins, while NMOS transistors use continuous fin lines to maintain high Ion current and fast speeds. This local differentiation allows each transistor type to be optimized for its specific function, resolving the contradiction between device stability and chip speed.
Data Source
AI summary
An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.