Discrete 3D Vertical Memory Segmentation for Cost Reduction
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Solution Overview
Problem
Integrated three-dimensional memory (3D-M) devices face high costs and low array efficiency due to the integration of peripheral circuits with memory arrays, which forces the use of expensive back-end-of-line (BEOL) manufacturing processes, increasing overall costs without reducing them.
Innovation Solution
A discrete 3D-MV design separates the 3D-array die and voltage-generator die into different components, allowing for optimized separate manufacturing and minimizing the peripheral circuit, with the voltage-generator die having fewer BEOL layers and lower wafer costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If integrated 3D-M devices are designed with peripheral circuits integrated with memory arrays, then functionality is complete, but manufacturing cost increases and array efficiency decreases
Solution Approach 1:
The patent divides the 3D-M device into separate components: a memory array die and a peripheral circuit die. The memory array die contains only the memory cells and address lines, while the peripheral circuit die contains decoders, sense amplifiers, and voltage generators. This segmentation allows each die to be optimized independently for its specific function, reducing manufacturing costs and improving array efficiency by eliminating the need for expensive BEOL processes in the memory array region.
2Reliability
If peripheral circuits are integrated with memory arrays in the same die, then device functionality is achieved, but BEOL manufacturing process complexity increases
Solution Approach 1:
The patent segments the device into two separate dies that are bonded together. The peripheral circuit die requires complex BEOL processes for decoders and sense amplifiers, while the memory array die uses a simpler BEOL structure. This segmentation allows the complex BEOL processes to be confined to a smaller area, reducing overall manufacturing complexity while maintaining complete device functionality through the bonded interface.
3Adaptability or versatility
If memory array and peripheral circuits share the same substrate, then device integration is achieved, but manufacturing cost increases
Solution Approach 1:
The patent uses segmentation to separate the memory array and peripheral circuits onto different substrates that are subsequently bonded. This approach maintains device integration at the system level while allowing each substrate to be manufactured independently with optimized processes, thereby reducing overall manufacturing cost compared to fabricating the entire device on a single substrate with the most complex process requirements.
4Productivity
If discrete 3D-MV design separates array die and voltage-generator die, then array efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by separating the 3D-array die from the voltage-generator die into distinct components. This segmentation improves array efficiency by allowing the 3D-array die to be densely packed with memory cells without the space requirements of voltage generation circuits. The increased device structure complexity is offset by the benefits of independent optimization and the use of standardized bonding interfaces.
Data Source
AI summary
The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a voltage-generator die. The 3D-array die comprises a plurality of vertical memory strings. At least a voltage-generator component for the 3D-array die is located on the voltage-generator die instead of the 3D-array die. The 3D-array die and the voltage-generator die have substantially different back-end-of-line (BEOL) structures.