Discrete 3D Vertical Memory Segmentation for BEOL Cost Reduction

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Solution Overview

Problem

Integrated three-dimensional vertical memory (3D-MV) devices face increased costs and performance degradation due to the need for expensive BEOL manufacturing processes and limited optimization of peripheral circuits, as they are integrated with the 3D-MV array, leading to inefficient use of resources and suboptimal performance.

Innovation Solution

A discrete 3D-MV design separates the 3D-MV array and address/data-translator into different dice, allowing for optimized BEOL structures and materials, reducing overall cost and improving performance by using fewer and higher-speed interconnect levels in the translator die compared to the array die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the 3D-MV array and peripheral circuits are integrated on the same die, then the device achieves compact integration, but the manufacturing cost increases and performance degrades due to incompatible BEOL processes

Engineering Contradiction:

Improveintegration compactnessVSAvoidmanufacturing cost

Core Design Contradiction:

Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent divides the memory device into two separate dice: a 3D-MV array die and a peripheral circuit die. This segmentation allows each die to be optimized independently with compatible BEOL processes, eliminating the manufacturing conflicts that arise from integrating incompatible circuits on the same die while maintaining compact form factor through stacking.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar integration to three-dimensional stacking by placing the peripheral circuit die above the 3D-MV array die and connecting them via through-silicon vias (TSVs). This dimensional change enables compact integration without the manufacturing conflicts of co-planar integration, as each die can use optimized, compatible processes.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If the 3D-MV array and peripheral circuits are integrated on the same die, then the device achieves compact integration, but the peripheral circuit performance degrades due to process compromises

Engineering Contradiction:

Improveintegration compactnessVSAvoidperipheral circuit performance

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

By separating the 3D-MV array and peripheral circuits onto different dice, each die can be manufactured with optimized BEOL processes tailored to its specific requirements. The peripheral circuit die can use processes optimized for high-performance logic circuits, while the 3D-MV array die uses processes optimized for memory cells, eliminating performance degradation from process compromises.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each die is manufactured with locally optimized BEOL structures and materials suited to its specific function. The peripheral circuit die receives optimized interconnect structures for high-speed logic operations, while the 3D-MV array die receives structures optimized for memory cell performance, ensuring each component achieves its best possible performance.

Inventive Principle:

Principle #3Local quality

3Volume of moving object

If the 3D-MV array and peripheral circuits are integrated on the same die, then the device achieves compact integration, but the BEOL structure complexity increases

Engineering Contradiction:

Improveintegration compactnessVSAvoidBEOL structure complexity

Core Design Contradiction:

Volume of moving objectVSDevice complexity

Solution Approach 1:

The BEOL structure is segmented into two separate, independently optimized structures on different dice. Each die has its own simplified BEOL design tailored to its specific requirements, avoiding the need for a single complex BEOL structure that must accommodate both memory array and peripheral circuit requirements simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent resolves BEOL complexity by moving to three-dimensional stacking, where each die has its own optimized BEOL structure. The inter-die connections are handled by TSVs, which simplify the overall architecture compared to attempting to integrate all circuits in a single plane with complex multi-layer interconnects.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Reliability

If expensive BEOL manufacturing processes are used for integration, then the device achieves high performance, but the manufacturing cost increases

Engineering Contradiction:

Improvedevice performanceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the device into two dice that can be manufactured using cost-effective, compatible BEOL processes appropriate for each die type. This avoids the need for expensive, complex integration processes while maintaining high performance through independent optimization of each die's BEOL structure.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9305604B2Discrete three-dimensional vertical memory comprising off-die address/data-translator

Publication Date: 2016.04.05 HANGZHOU HAICUN INFORMATION TECHNOLOGY CO LTD

AI summary

The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least an A/D-translator die. The 3D-array die comprises a plurality of vertical memory strings. At least an address/data (A/D)-translator for the 3D-array die is located on the A/D-translator die instead of the 3D-array die. The 3D-array die and the A/D-translator die have substantially different back-end-of-line (BEOL) structures.